Yang Zhao

Orcid: 0000-0001-8023-1551

Affiliations:
  • Georgia Institute of Technology, Atlanta, GA, USA
  • Rice University, Department of Electrical and Computer Engineering, Houston, TX, USA (PhD)
  • Fudan University, State Key Laboratory of ASIC and Systems, Shanghai, China (former)


According to our database1, Yang Zhao authored at least 70 papers between 2013 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

Online presence:

On csauthors.net:

Bibliography

2026
Discrete Diffusion for Complex and Congested Multi-Agent Path Finding with Sparse Social Attention.
CoRR, May, 2026

CodeV: Empowering LLMs With HDL Generation Through Multilevel Summarization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2026

Gaussians on a Diet: High-Quality Memory-Bounded 3D Gaussian Splatting Training.
CoRR, April, 2026

HDLxGraph: Bridging Large Language Models and HDL Repositories via HDL Graph Databases.
Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026

2025
Towards Physics-informed Spatial Intelligence with Human Priors: An Autonomous Driving Pilot Study.
CoRR, October, 2025

How to Auto-optimize Prompts for Domain Tasks? Adaptive Prompting and Reasoning through Evolutionary Domain Knowledge Adaptation.
CoRR, October, 2025

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs.
CoRR, July, 2025

Advancing real-time infectious disease forecasting using large language models.
Nat. Comput. Sci., June, 2025

CodeV-R1: Reasoning-Enhanced Verilog Generation.
CoRR, May, 2025

HDLxGraph: Bridging Large Language Models and HDL Repositories via HDL Graph Databases.
CoRR, May, 2025

Occult: Optimizing Collaborative Communication across Experts for Accelerated Parallel MoE Training and Inference.
CoRR, May, 2025

Towards Reliable and Interpretable Traffic Crash Pattern Prediction and Safety Interventions Using Customized Large Language Models.
CoRR, May, 2025

MixGCN: Scalable GCN Training by Mixture of Parallelism and Mixture of Accelerators.
CoRR, January, 2025

QiMeng-CodeV-R1: Reasoning-Enhanced Verilog Generation.
Proceedings of the Advances in Neural Information Processing Systems 38: Annual Conference on Neural Information Processing Systems 2025, 2025

Personalized Decision Modeling: Utility Optimization or Textualized-Symbolic Reasoning.
Proceedings of the Advances in Neural Information Processing Systems 38: Annual Conference on Neural Information Processing Systems 2025, 2025

Mozart: Modularized and Efficient MoE Training on 3.5D Wafer-Scale Chiplet Architectures.
Proceedings of the Advances in Neural Information Processing Systems 38: Annual Conference on Neural Information Processing Systems 2025, 2025

RTGS: Real-Time 3D Gaussian Splatting SLAM via Multi-Level Redundancy Reduction.
Proceedings of the 58th IEEE/ACM International Symposium on Microarchitecture, 2025

Generative AI in Embodied Systems: System-Level Analysis of Performance, Efficiency and Scalability.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2025

Occult: Optimizing Collaborative Communications across Experts for Accelerated Parallel MoE Training and Inference.
Proceedings of the Forty-second International Conference on Machine Learning, 2025

MAHL: Multi-Agent LLM-Guided Hierarchical Chiplet Design with Adaptive Debugging.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2025

ReCA: Integrated Acceleration for Real-Time and Efficient Cooperative Embodied Autonomous Agents.
Proceedings of the 30th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2025

2024
AutoAI2C: An Automated Hardware Generator for DNN Acceleration on Both FPGA and ASIC.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2024

HiVeGen - Hierarchical LLM-based Verilog Generation for Scalable Chip Design.
CoRR, 2024

CodeV: Empowering LLMs for Verilog Generation through Multi-Level Summarization.
CoRR, 2024

EDGE-LLM: Enabling Efficient Large Language Model Adaptation on Edge Devices via Layerwise Unified Compression and Adaptive Layer Tuning and Voting.
CoRR, 2024

Learning Traffic Crashes as Language: Datasets, Benchmarks, and What-if Causal Analyses.
CoRR, 2024

Advancing Real-time Pandemic Forecasting Using Large Language Models: A COVID-19 Case Study.
CoRR, 2024

Fusion-3D: Integrated Acceleration for Instant 3D Reconstruction and Real-Time Rendering.
Proceedings of the 57th IEEE/ACM International Symposium on Microarchitecture, 2024

Mitigating Bias of Deep Neural Networks for Trustworthy Traffic Perception in Autonomous Systems.
Proceedings of the IEEE Intelligent Vehicles Symposium, 2024

Thinking and Moving: An Efficient Computing Approach for Integrated Task and Motion Planning in Cooperative Embodied AI Systems.
Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024

R-DUCT: Robust Dynamic Unified Carbon Modeling Tool Under Severe Uncertainty.
Proceedings of the 15th IEEE International Green and Sustainable Computing Conference, 2024

U-DUCT: Uncertainty-aware Dynamic Unified Carbon Modeling Tool for Datacenter Scheduling.
Proceedings of the 15th IEEE International Green and Sustainable Computing Conference, 2024

3D-Carbon: An Analytical Carbon Modeling Tool for 3D and 2.5D Integrated Circuits.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

EDGE-LLM: Enabling Efficient Large Language Model Adaptation on Edge Devices via Unified Compression and Adaptive Layer Voting.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023
SmartDeal: Remodeling Deep Network Weights for Efficient Inference and Training.
IEEE Trans. Neural Networks Learn. Syst., October, 2023

EyeCoD: Eye Tracking System Acceleration via FlatCam-Based Algorithm and Hardware Co-Design.
IEEE Micro, 2023

Instant-3D: Instant Neural Radiance Field Training Towards On-Device AR/VR 3D Reconstruction.
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

ViTCoD: Vision Transformer Acceleration via Dedicated Algorithm and Accelerator Co-Design.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

Instant-NeRF: Instant On-Device Neural Radiance Field Training via Algorithm-Accelerator Co-Designed Near-Memory Processing.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022
PushBox: Making Use of Every Bit of Time to Accelerate Completion of Data-Parallel Jobs.
IEEE Trans. Parallel Distributed Syst., 2022

e-G2C: A 0.14-to-8.31 µJ/Inference NN-based Processor with Continuous On-chip Adaptation for Anomaly Detection and ECG Conversion from EGM.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

i-FlatCam: A 253 FPS, 91.49 µJ/Frame Ultra-Compact Intelligent Lensless Camera for Real-Time and Efficient Eye Tracking in VR/AR.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

EyeCoD: eye tracking system acceleration via flatcam-based algorithm & accelerator co-design.
Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022

NASA: Neural Architecture Search and Acceleration for Hardware Inspired Hybrid Networks.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

RT-NeRF: Real-Time On-Device Neural Radiance Fields Towards Immersive AR/VR Rendering.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

2021
Practical Attacks on Deep Neural Networks by Memory Trojaning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

HW-NAS-Bench: Hardware-Aware Neural Architecture Search Benchmark.
CoRR, 2021

SmartDeal: Re-Modeling Deep Network Weights for Efficient Inference and Training.
CoRR, 2021

2-in-1 Accelerator: Enabling Random Precision Switch for Winning Both Adversarial Robustness and Efficiency.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

HW-NAS-Bench: Hardware-Aware Neural Architecture Search Benchmark.
Proceedings of the 9th International Conference on Learning Representations, 2021

2020
FracTrain: Fractionally Squeezing Bit Savings Both Temporally and Spatially for Efficient DNN Training.
Proceedings of the Advances in Neural Information Processing Systems 33: Annual Conference on Neural Information Processing Systems 2020, 2020

A New MRAM-Based Process In-Memory Accelerator for Efficient Neural Network Training with Floating Point Precision.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

SmartExchange: Trading Higher-cost Memory Storage/Access for Lower-cost Computation.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

Timely: Pushing Data Movements And Interfaces In Pim Accelerators Towards Local And In Time Domain.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architectures.
Proceedings of the 2020 IEEE International Conference on Acoustics, 2020

AutoDNNchip: An Automated DNN Chip Predictor and Builder for Both FPGAs and ASICs.
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

2019
E2-Train: Energy-Efficient Deep Network Training with Data-, Model-, and Algorithm-Level Saving.
CoRR, 2019

E2-Train: Training State-of-the-art CNNs with Over 80% Energy Savings.
Proceedings of the Advances in Neural Information Processing Systems 32: Annual Conference on Neural Information Processing Systems 2019, 2019

Live Demonstration: Bringing Powerful Deep Learning into Daily-Life Devices (Mobiles and FPGAs) Via Deep k-Means.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Memory Trojan Attack on Neural Network Accelerators.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

A Low-Cost and Energy-Efficient NoC Architecture for GPGPUs.
Proceedings of the 2019 ACM/IEEE Symposium on Architectures for Networking and Communications Systems, 2019

2018
SCAPE: Safe Charging With Adjustable Power.
IEEE/ACM Trans. Netw., 2018

Robustly Safe Charging for Wireless Power Transfer.
Proceedings of the 2018 IEEE Conference on Computer Communications, 2018

Packet pump: overcoming network bottleneck in on-chip interconnects for GPGPUs.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
Performance of Container Networking Technologies.
Proceedings of the Workshop on Hot Topics in Container Networking and Networked Systems, 2017

Radiation Constrained Fair Wireless Charging.
Proceedings of the 14th Annual IEEE International Conference on Sensing, 2017

2016
An All-Digital Gigahertz Class-S Transmitter in a 65-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Omnidirectional chargability with directional antennas.
Proceedings of the 24th IEEE International Conference on Network Protocols, 2016

2015
An all-digital quadrature RF transmitter with 8-bit ΣΔ modulation.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2013
Design of a time-interleaved band-pass ΣΔ modulator for Class-S power amplifier.
Proceedings of the IEEE 10th International Conference on ASIC, 2013


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