Shuyao Cheng

According to our database, Shuyao Cheng authored at least 22 papers between 2016 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

DASA: Distribution-Aware Sparse Attention for Accelerating Diffusion Transformer.

Tianyun Ma, Jiaming Guo, Di Huang, Xinkai Song, Qian Wang, Husheng Han, Pengwei Jin, Xiangtao Guan, Yifan Hao, Yuanbo Wen, Shuyao Cheng, Zidong Du, Rui Zhang, Xing Hu, Qi Guo

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2026

AGON: Automated Design Framework for Customizing Processors From ISA Documents.

Chongxiao Li, Di Huang, Pengwei Jin, Tianyun Ma, Husheng Han, Shuyao Cheng, Yifan Hao, Yongwei Zhao, Guanglin Xu, Zidong Du, Rui Zhang, Xiaqing Li, Yuanbo Wen, Xing Hu, Qi Guo

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2026

AutoPPA: Automated Circuit PPA Optimization via Contrastive Code-based Rule Library Learning.

Chongxiao Li, Pengwei Jin, Di Huang, Guangrun Sun, Husheng Han, Jianan Mu, Xinyao Zheng, Jiaguo Zhu, Shuyi Xing, Hanjun Wei, Tianyun Ma, Shuyao Cheng, Rui Zhang, Ying Wang, Zidong Du, Qi Guo, Xing Hu

CoRR, April, 2026

LocalV: Exploiting Information Locality for IP-level Verilog Generation.

Han-Qi Lyu, Di Huang, Yaoyu Zhu, Kangcheng Liu, Bohan Dou, Chongxiao Li, Pengwei Jin, Shuyao Cheng, Rui Zhang, Zidong Du, Qi Guo, Xing Hu, Yunji Chen

CoRR, February, 2026

Data-Driven Automated Processor Design.

Xiangtao Guan, Shuyao Cheng, Mo Zou, Rui Zhang, Yun-Ji Chen

J. Comput. Sci. Technol., January, 2026

QiMeng-CRUX: Narrowing the Gap Between Natural Language and Verilog via Core Refined Understanding eXpression.

Lei Huang, Rui Zhang, Jiaming Guo, Yang Zhang, Di Huang, Shuyao Cheng, Pengwei Jin, Chongxiao Li, Zidong Du, Xing Hu, Yunji Chen, Qi Guo

Proceedings of the Fortieth AAAI Conference on Artificial Intelligence, 2026

2025

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs.

Pengwei Jin, Di Huang, Chongxiao Li, Shuyao Cheng, Yang Zhao, Xinyao Zheng, Jiaguo Zhu, Shuyi Xing, Bohan Dou, Rui Zhang, Zidong Du, Qi Guo, Xing Hu

CoRR, July, 2025

QiMeng: Fully Automated Hardware and Software Design for Processor Chip.

Rui Zhang, Yuanbo Wen, Shuyao Cheng, Di Huang, Shaohui Peng, Jiaming Guo, Pengwei Jin, Jiacheng Zhao, Tianrui Ma, Yaoyu Zhu, Yifan Hao, Yongwei Zhao, Shengwen Liang, Ying Wang, Xing Hu, Zidong Du, Huimin Cui, Ling Li, Qi Guo, Yunji Chen

CoRR, June, 2025

CodeV-R1: Reasoning-Enhanced Verilog Generation.

Yaoyu Zhu, Di Huang, Han-Qi Lyu, Xiaoyun Zhang, Chongxiao Li, Wenxuan Shi, Yutong Wu, Jianan Mu, Jinghua Wang, Yang Zhao, Pengwei Jin, Shuyao Cheng, Shengwen Liang, Xishan Zhang, Rui Zhang, Zidong Du, Qi Guo, Xing Hu, Yunji Chen

CoRR, May, 2025

QiMeng-CPU-v2: Automated Superscalar Processor Design by Learning Data Dependencies.

Shuyao Cheng, Rui Zhang, Wenkai He, Pengwei Jin, Chongxiao Li, Zidong Du, Xing Hu, Yifan Hao, Guanglin Xu, Yuanbo Wen, Ling Li, Qi Guo, Yunji Chen

CoRR, May, 2025

QiMeng-CodeV-R1: Reasoning-Enhanced Verilog Generation.

Yaoyu Zhu, Di Huang, Han-Qi Lyu, Xiaoyun Zhang, Chongxiao Li, Wenxuan Shi, Yutong Wu, Jianan Mu, Jinghua Wang, Yang Zhao, Pengwei Jin, Shuyao Cheng, Shengwen Liang, Xishan Zhang, Rui Zhang, Zidong Du, Qi Guo, Xing Hu, Yunji Chen

Proceedings of the Advances in Neural Information Processing Systems 38: Annual Conference on Neural Information Processing Systems 2025, 2025

QiMeng-SALV: Signal-Aware Learning for Verilog Code Generation.

Yang Zhang, Rui Zhang, Jiaming Guo, Lei Huang, Di Huang, Yunpu Zhao, Shuyao Cheng, Pengwei Jin, Chongxiao Li, Zidong Du, Xing Hu, Qi Guo, Yunji Chen

Proceedings of the Advances in Neural Information Processing Systems 38: Annual Conference on Neural Information Processing Systems 2025, 2025

Automated Superscalar Processor Design by Learning Data Dependencies.

Shuyao Cheng, Rui Zhang, Wenkai He, Pengwei Jin, Chongxiao Li, Zidong Du, Xing Hu, Yifan Hao, Guanglin Xu, Yuanbo Wen, Ling Li, Qi Guo, Yunji Chen

Proceedings of the Thirty-Fourth International Joint Conference on Artificial Intelligence, 2025

Area-Efficient Automated Logic Design with Monte-Carlo Tree Search.

Shuyao Cheng, Xiangtao Guan, Zidong Du

Proceedings of the Advanced Parallel Processing Technologies, 2025

2024

AGON: Automated Design Framework for Customizing Processors from ISA Documents.

Chongxiao Li, Di Huang, Pengwei Jin, Tianyun Ma, Husheng Han, Shuyao Cheng, Yifan Hao, Yongwei Zhao, Guanglin Xu, Zidong Du, Rui Zhang, Xiaqing Li, Yuanbo Wen, Yanjun Wu, Chen Zhao, Xing Hu, Qi Guo

CoRR, 2024

Automated CPU Design by Learning from Input-Output Examples.

Shuyao Cheng, Pengwei Jin, Qi Guo, Zidong Du, Rui Zhang, Xing Hu, Yongwei Zhao, Yifan Hao, Xiangtao Guan, Husheng Han, Zhengyue Zhao, Ximing Liu, Xishan Zhang, Yuejie Chu, Weilong Mao, Tianshi Chen, Yunji Chen

Proceedings of the Thirty-Third International Joint Conference on Artificial Intelligence, 2024

Revisiting Automatic Pipelining: Gate-level Forwarding and Speculation.

Shuyao Cheng, Chongxiao Li, Zidong Du, Rui Zhang, Xing Hu, Xiaqing Li, Guanglin Xu, Yuanbo Wen, Qi Guo

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023

Pushing the Limits of Machine Design: Automated CPU Design with AI.

Shuyao Cheng, Pengwei Jin, Qi Guo, Zidong Du, Rui Zhang, Yunhao Tian, Xing Hu, Yongwei Zhao, Yifan Hao, Xiangtao Guan, Husheng Han, Zhengyue Zhao, Ximing Liu, Ling Li, Xishan Zhang, Yuejie Chu, Weilong Mao, Tianshi Chen, Yunji Chen

CoRR, 2023

2022

Cambricon-P: A Bitflow Architecture for Arbitrary Precision Computing.

Yifan Hao, Yongwei Zhao, Chenxiao Liu, Zidong Du, Shuyao Cheng, Xiaqing Li, Xing Hu, Qi Guo, Zhiwei Xu, Tianshi Chen

Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

2019

BSHIFT: A Low Cost Deep Neural Networks Accelerator.

Yong Yu, Tian Zhi, Xuda Zhou, Shaoli Liu, Yunji Chen, Shuyao Cheng

Int. J. Parallel Program., 2019

2018

Decentralized Fault Tolerant Control for a Class of Interconnected Nonlinear Systems.

Shuai Shao, Hao Yang, Bin Jiang, Shuyao Cheng

IEEE Trans. Cybern., 2018

2016

An integrated fault estimation and accommodation design for a class of complex networks.

Shuyao Cheng, Hao Yang, Bin Jiang

Neurocomputing, 2016