Jianan Mu

According to our database, Jianan Mu authored at least 5 papers between 2022 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Scalable and Conflict-Free NTT Hardware Accelerator Design: Methodology, Proof, and Implementation.

Jianan Mu, Yi Ren, Wen Wang, Yizhong Hu, Shuai Chen, Chip-Hong Chang, Junfeng Fan, Jing Ye, Yuan Cao, Huawei Li, Xiaowei Li

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2023

Online Reliability Evaluation Design: Select Reliable CRPs for Arbiter PUF and Its Variants.

Chaofang Ma, Jianan Mu, Jing Ye, Shuai Chen, Yuan Cao, Huawei Li, Xiaowei Li

Proceedings of the IEEE European Test Symposium, 2023

Energy-efficient NTT Design with One-bank SRAM and 2-D PE Array.

Jianan Mu, Huajie Tan, Jiawen Wu, Haotian Lu, Chip-Hong Chang, Shuai Chen, Shengwen Liang, Jing Ye, Huawei Li, Xiaowei Li

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Configurable and High-Level Pipelined Lattice-Based Post Quantum Cryptography Hardware Accelerator Design.

Jianan Mu, Huajie Tan, Shuai Chen, Min Cai, Jing Ye, Huawei Li, Xiaowei Li

Proceedings of the 32nd IEEE Asian Test Symposium, 2023

2022

A Voltage Template Attack on the Modular Polynomial Subtraction in Kyber.

Jianan Mu, Yixuan Zhao, Zongyue Wang, Jing Ye, Junfeng Fan, Shuai Chen, Huawei Li, Xiaowei Li, Yuan Cao

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022