Christian Benkeser

According to our database1, Christian Benkeser authored at least 27 papers between 2007 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2015
On the Mapping of Incremental Redundancy into a Physical Layer ASIC.
J. Signal Process. Syst., 2015

An Evolved GSM/EDGE Baseband ASIC Supporting Rx Diversity.
IEEE J. Solid State Circuits, 2015

2014
Efficient Parallel Turbo-Decoding for High-Throughput Wireless Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Power-efficient turbo-decoder design based on algorithm-specific power domain partitioning.
Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014

A 1.9 GS/s 4-bit sub-Nyquist flash ADC for 3.8 GHz compressive spectrum sensing in 28 nm CMOS.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

Compressive sensing spectrum recovery from quantized measurements in 28nm SOI CMOS.
Proceedings of the 22nd European Signal Processing Conference, 2014

An evolved EDGE PHY ASIC supporting soft-output equalization and Rx diversity.
Proceedings of the ESSCIRC 2014, 2014

2013
Physical Layer Development Framework for OsmocomBB.
J. Signal Process. Syst., 2013

VLSI Design of a Monolithic Compressive-Sensing Wideband Analog-to-Information Converter.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2013

Digital front-end design for carrier aggregation in next-generation cellular user equipment.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

Efficient vlsi implementation of reduced-state sequence estimation for wireless communications.
Proceedings of the IEEE International Conference on Acoustics, 2013

2012
Implementation Trade-Offs of Soft-Input Soft-Output MAP Decoders for Convolutional Codes.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

Turbo decoder design for high code rates.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

Successive interference cancellation for 3G downlink: Algorithm and VLSI architecture.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

A novel constrained-Viterbi algorithm with linear equalization and grouping assistance.
Proceedings of the 2012 International Symposium on Wireless Communication Systems (ISWCS), 2012

Efficient channel shortening for higher order modulation: Algorithm and architecture.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Low-complexity frequency synchronization for GSM systems: Algorithms and implementation.
Proceedings of the 4th International Congress on Ultra Modern Telecommunications and Control Systems, 2012

On the exploitation of the inherent error resilience of wireless systems under unreliable silicon.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Data mapping for unreliable memories.
Proceedings of the 50th Annual Allerton Conference on Communication, 2012

2011
Design and Implementation of a Parallel Turbo-Decoder ASIC for 3GPP-LTE.
IEEE J. Solid State Circuits, 2011

2010
Design and Optimization of a Digital Baseband Receiver ASIC for GSM/EDGE.
Proceedings of the VLSI-SoC: Forward-Looking Trends in IC and Systems Design, 2010

A 1mm<sup>2</sup> 1.3mW GSM/EDGE digital baseband receiver ASIC in 0.13 µm CMOS.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

A 390Mb/s 3.57mm<sup>2</sup> 3GPP-LTE turbo decoder ASIC in 0.13µm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A 4.5mW digital baseband receiver for level-A evolved EDGE.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009
Design and Optimization of an HSDPA Turbo Decoder ASIC.
IEEE J. Solid State Circuits, 2009

2008
A 58mW 1.2mm<sup>2</sup> HSDPA Turbo Decoder ASIC in 0.13μm CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007
A 50mW HSDPA Baseband Receiver ASIC with Multimode Digital Front-End.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007


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