Andreas Peter Burg

According to our database1, Andreas Peter Burg authored at least 163 papers between 2003 and 2019.

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2019
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory.
IEEE Trans. VLSI Syst., 2019

3.5 GHz Coverage Assessment with a 5G Testbed.
Proceedings of the 89th IEEE Vehicular Technology Conference, 2019

A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

Data-Retention-Time Characterization of Gain-Cell eDRAMs Across the Design and Variations Space.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Lora Digital Receiver Analysis and Implementation.
Proceedings of the IEEE International Conference on Acoustics, 2019

FPGA-Based Emulation of Embedded DRAMs for Statistical Error Resilience Evaluation of Approximate Computing Systems.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
A 588-Gb/s LDPC Decoder Based on Finite-Alphabet Message Passing.
IEEE Trans. VLSI Syst., 2018

Design Techniques for High-Speed Multi-Level Viterbi Detectors and Trellis-Coded-Modulation Decoders.
IEEE Trans. on Circuits and Systems, 2018

A 4-Transistor nMOS-Only Logic-Compatible Gain-Cell Embedded DRAM With Over 1.6-ms Retention Time at 700 mV in 28-nm FD-SOI.
IEEE Trans. on Circuits and Systems, 2018

Wireless Communication and Security Issues for Cyber-Physical Systems and the Internet-of-Things.
Proceedings of the IEEE, 2018

An 800-MHz Mixed- VT 4T IFGC Embedded DRAM in 28-nm CMOS Bulk Process for Approximate Storage Applications.
J. Solid-State Circuits, 2018

Fast-SSC-flip decoding of polar codes.
Proceedings of the 2018 IEEE Wireless Communications and Networking Conference Workshops, 2018

On the Tradeoff Between Accuracy and Complexity in Blind Detection of Polar Codes.
Proceedings of the 10th IEEE International Symposium on Turbo Codes & Iterative Information Processing, 2018

A Timing-Monitoring Sequential for Forward and Backward Error-Detection in 28 nm FD-SOI.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Design and Implementation of a Neural Network Aided Self-Interference Cancellation Scheme for Full-Duplex Radios.
Proceedings of the 52nd Asilomar Conference on Signals, Systems, and Computers, 2018

2017
An FPGA-Based 4 Mbps Secret Key Distillation Engine for Quantum Key Distribution Systems.
Signal Processing Systems, 2017

Automated Integration of Dual-Edge Clocking for Low-Power Operation in Nanometer Nodes.
ACM Trans. Design Autom. Electr. Syst., 2017

Multipliers-Driven Perturbation of Coefficients for Low-Power Operation in Reconfigurable FIR Filters.
IEEE Trans. on Circuits and Systems, 2017

Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster.
IEEE Micro, 2017

PolarBear: A 28-nm FD-SOI ASIC for Decoding of Polar Codes.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2017

A Self-Aware Architecture for PVT Compensation and Power Nap in Near Threshold Processors.
IEEE Design & Test, 2017

Comparison of Polar Decoders with Existing Low-Density Parity-Check and Turbo Decoders.
Proceedings of the 2017 IEEE Wireless Communications and Networking Conference Workshops, 2017

Blind detection of polar codes.
Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017

DVFS based power management for LDPC decoders with early termination.
Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017

Digital predistortion of hardware impairments for full-duplex transceivers.
Proceedings of the 2017 IEEE Global Conference on Signal and Information Processing, 2017

An 800 Mhz mixed-VT 4T gain-cell embedded DRAM in 28 nm CMOS bulk process for approximate computing applications.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

Full-duplex communications for wireless links with asymmetric capacity requirements.
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017

2016
Cross-Layer Energy-Efficiency Optimization of Packet Based Wireless MIMO Communication Systems.
Signal Processing Systems, 2016

Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications.
IEEE Trans. VLSI Syst., 2016

Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement.
ACM Trans. Design Autom. Electr. Syst., 2016

Silicon-Proven, Per-Cell Retention Time Distribution Model for Gain-Cell Based eDRAMs.
IEEE Trans. on Circuits and Systems, 2016

Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65 nm CMOS.
IEEE Trans. on Circuits and Systems, 2016

Sliding Window Spectrum Sensing for Full-Duplex Cognitive Radios with Low Access-Latency.
Proceedings of the IEEE 83rd Vehicular Technology Conference, 2016

Digital predistortion of power amplifier non-linearities for full-duplex transceivers.
Proceedings of the 17th IEEE International Workshop on Signal Processing Advances in Wireless Communications, 2016

A process compensated gain cell embedded-DRAM for ultra-low-power variation-aware design.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Hardware decoders for polar codes: An overview.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A low-power correlator for wakeup receivers with algorithm pruning through early termination.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Experimental signal-quality characterization of a high-capacity mmWave link for backhaul applications.
Proceedings of the 2016 IEEE Sensor Array and Multichannel Signal Processing Workshop (SAM), 2016

Design considerations on sliding-block viterbi detectors for high-speed data transmission.
Proceedings of the 10th International Conference on Signal Processing and Communication Systems, 2016

A 4.1 pJ/b 25.6 Gb/s 4-PAM reduced-state sliding-block Viterbi detector in 14 nm CMOS.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

DynOR: A 32-bit microprocessor in 28 nm FD-SOI with cycle-by-cycle dynamic clock adjustment.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

Approximate computing for unreliable silicon.
Proceedings of the 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016

Energy vs. reliability trade-offs exploration in biomedical ultra-low power devices.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Statistical fault injection for impact-evaluation of timing errors on application performance.
Proceedings of the 53rd Annual Design Automation Conference, 2016

High-speed link with trellis-coded modulation and Reed-Solomon coding.
Proceedings of the 2016 IEEE Conference on Standards for Communications and Networking, 2016

193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing.
Proceedings of the 2016 IEEE Symposium in Low-Power and High-Speed Chips, 2016

A multi-Gbps unrolled hardware list decoder for a systematic polar code.
Proceedings of the 50th Asilomar Conference on Signals, Systems and Computers, 2016

2015
Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs.
ACM Trans. Embedded Comput. Syst., 2015

An Evolved GSM/EDGE Baseband ASIC Supporting Rx Diversity.
J. Solid-State Circuits, 2015

Baseband and RF hardware impairments in full-duplex wireless systems: experimental characterisation and suppression.
EURASIP J. Wireless Comm. and Networking, 2015

Channel shortening and equalization based on information rate maximization for evolved GSM/EDGE.
Proceedings of the 2015 IEEE Workshop on Signal Processing Systems, 2015

A fully-unrolled LDPC decoder based on quantized message passing.
Proceedings of the 2015 IEEE Workshop on Signal Processing Systems, 2015

Approximate computing with unreliable dynamic memories.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

Demo: Concurrent Spectrum Sensing and Transmission for Cognitive Radio using Self-Interference Cancellation.
Proceedings of the 16th ACM International Symposium on Mobile Ad Hoc Networking and Computing, 2015

Refresh-free dynamic standard-cell based memories: Application to a QC-LDPC decoder.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

An overlap-contention free true-single-phase clock dual-edge-triggered flip-flop.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

On metric sorting for successive cancellation list decoding of polar codes.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

An FPGA-based accelerator for rapid simulation of SC decoding of polar codes.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

Digital synchronization for symbol-spaced IEEE802.11ad Gigabit mmWave systems.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

A 3.6pJ/b 56Gb/s 4-PAM receiver with 6-Bit TI-SAR ADC and quarter-rate speculative 2-tap DFE in 32 nm CMOS.
Proceedings of the ESSCIRC Conference 2015, 2015

Energy versus data integrity trade-offs in embedded high-density logic compatible dynamic memories.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Exploiting dynamic timing margins in microprocessors for frequency-over-scaling with instruction-based clock adjustment.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

On the statistical memory architecture exploration and optimization.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Mitigating the impact of faults in unreliable memories for error-resilient applications.
Proceedings of the 52nd Annual Design Automation Conference, 2015

A 3.52 Gb/s mmWave baseband with delayed decision feedback sequence estimation in 40 nm.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

Controlled placement of standard cell memory arrays for high density and low power in 28nm FD-SOI.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

Energy-proportional single-carrier frequency domain equalization for mmWave wireless communication.
Proceedings of the 49th Asilomar Conference on Signals, Systems and Computers, 2015

The impact of faulty memory bit cells on the decoding of spatially-coupled LDPC codes.
Proceedings of the 49th Asilomar Conference on Signals, Systems and Computers, 2015

Quantized message passing for LDPC codes.
Proceedings of the 49th Asilomar Conference on Signals, Systems and Computers, 2015

2014
Replica Technique for Adaptive Refresh Timing of Gain-Cell-Embedded DRAM.
IEEE Trans. on Circuits and Systems, 2014

A Lattice Reduction-Aided MIMO Channel Equalizer in 90 nm CMOS Achieving 720 Mb/s.
IEEE Trans. on Circuits and Systems, 2014

Energy/Reliability Trade-Offs in Low-Voltage ReRAM-Based Non-Volatile Flip-Flop Design.
IEEE Trans. on Circuits and Systems, 2014

Hardware Architecture for List Successive Cancellation Decoding of Polar Codes.
IEEE Trans. on Circuits and Systems, 2014

Density Evolution for Min-Sum Decoding of LDPC Codes Under Unreliable Message Storage.
IEEE Communications Letters, 2014

Energy Efficiency through Significance-Based Computing.
IEEE Computer, 2014

Faulty successive cancellation decoding of polar codes for the binary erasure channel.
Proceedings of the International Symposium on Information Theory and its Applications, 2014

Enabling complexity-performance trade-offs for successive cancellation decoding of polar codes.
Proceedings of the 2014 IEEE International Symposium on Information Theory, Honolulu, HI, USA, June 29, 2014

A signal processor for Gaussian message passing.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

4T Gain-Cell with internal-feedback for ultra-low retention power at scaled CMOS nodes.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Measurement-based characterization of residual self-interference on a full-duplex MIMO testbed.
Proceedings of the IEEE 8th Sensor Array and Multichannel Signal Processing Workshop, 2014

Cross layer energy-efficiency optimization for cognitive radio transceivers.
Proceedings of the IEEE International Conference on Acoustics, 2014

Robust asynchronous indoor localization using LED lighting.
Proceedings of the IEEE International Conference on Acoustics, 2014

LLR-based successive cancellation list decoding of polar codes.
Proceedings of the IEEE International Conference on Acoustics, 2014

FPGA implementation of an interior point method for high-speed model predictive control.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

A Wireless Body Sensor Network for Activity Monitoring with Low Transmission Overhead.
Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, 2014

An evolved EDGE PHY ASIC supporting soft-output equalization and Rx diversity.
Proceedings of the ESSCIRC 2014, 2014

A quality-scalable and energy-efficient approach for spectral analysis of heart rate variability.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Data compression via logic synthesis.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

Statistical data correction for unreliable memories.
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014

On the performance of LDPC and turbo decoder architectures with unreliable memories.
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014

A low-complexity improved successive cancellation decoder for polar codes.
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014

2013
A ReRAM-based non-volatile flip-flop with sub-VT read and CMOS voltage-compatible write.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

A parallelized layered QC-LDPC decoder for IEEE 802.11ad.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

Live demonstration: Real-time audio restoration using sparse signal recovery.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Block-floating-point enhanced MMSE filter matrix computation for MIMO-OFDM communication systems.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

A multipurpose testbed for full-duplex wireless communications.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

Efficient vlsi implementation of reduced-state sequence estimation for wireless communications.
Proceedings of the IEEE International Conference on Acoustics, 2013

Synchronizing code execution on ultra-low-power embedded multi-channel signal analysis platforms.
Proceedings of the Design, Automation and Test in Europe, 2013

Fast and accurate BER estimation methodology for I/O links based on extreme value theory.
Proceedings of the Design, Automation and Test in Europe, 2013

FireBird: PowerPC e200 based SoC for high temperature operation.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

Channel-optimized vector quantization with mutual information as fidelity criterion.
Proceedings of the 2013 Asilomar Conference on Signals, 2013

On self-interference suppression methods for low-complexity full-duplex MIMO.
Proceedings of the 2013 Asilomar Conference on Signals, 2013

2012
Analysis and VLSI Implementation of EWA Rendering for Real-Time HD Video Applications.
IEEE Trans. Circuits Syst. Video Techn., 2012

Low-power processor architecture exploration for online biomedical signal analysis.
IET Circuits, Devices & Systems, 2012

Investigating the Potential of Custom Instruction Set Extensions for SHA-3 Candidates on a 16-bit Microcontroller Architecture.
IACR Cryptology ePrint Archive, 2012

VLSI Design of Approximate Message Passing for Signal Restoration and Compressive Sensing.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

An Ultra-Low-Power Application-Specific Processor with Sub-VT Memories for Compressed Sensing.
Proceedings of the VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design, 2012

TamaRISC-CS: An ultra-low-power application-specific processor for compressed sensing.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

Successive interference cancellation for 3G downlink: Algorithm and VLSI architecture.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

Replica bit-line technique for embedded multilevel gain-cell DRAM.
Proceedings of the 10th IEEE International NEWCAS Conference, 2012

A novel constrained-Viterbi algorithm with linear equalization and grouping assistance.
Proceedings of the 2012 International Symposium on Wireless Communication Systems (ISWCS), 2012

Hardware-efficient random sampling of fourier-sparse signals.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Two-port low-power gain-cell storage array: Voltage scaling and retention time.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Low-complexity frequency synchronization for GSM systems: Algorithms and implementation.
Proceedings of the 4th International Congress on Ultra Modern Telecommunications and Control Systems, 2012

Shortening Design Time through Multiplatform Simulations with a Portable OpenCL Golden-model: The LDPC Decoder Case.
Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-VT memory in 65nm CMOS.
Proceedings of the 38th European Solid-State Circuit conference, 2012

A 2.78 mm2 65 nm CMOS gigabit MIMO iterative detection and decoding receiver.
Proceedings of the 38th European Solid-State Circuit conference, 2012

Multi-core architecture design for ultra-low-power wearable health monitoring systems.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Layered detection and decoding in MIMO wireless systems.
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012

Sparsity-based real-time audio restoration.
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012

On the exploitation of the inherent error resilience of wireless systems under unreliable silicon.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Design of energy efficient and dependable health monitoring systems under unreliable nanometer technologies.
Proceedings of the 7th International Conference on Body Area Networks, 2012

Instruction Set Extensions for Cryptographic Hash Functions on a Microcontroller Architecture.
Proceedings of the 23rd IEEE International Conference on Application-Specific Systems, 2012

Data mapping for unreliable memories.
Proceedings of the 50th Annual Allerton Conference on Communication, 2012

Session MP8a1: MIMO communications and signal processing I.
Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012

Low-complexity vector precoding for multi-user systems.
Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012

2011
Computational stereo camera system with programmable control loop.
ACM Trans. Graph., 2011

Benchmarking of Standard-Cell Based Memories in the Sub- VT Domain in 65-nm CMOS Technology.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011

An FPGA-based processing pipeline for high-definition stereo video.
EURASIP J. Image and Video Processing, 2011

Power/Performance Exploration of Single-core and Multi-core Processor Approaches for Biomedical Signal Processing.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011

Area, throughput, and energy-efficiency trade-offs in the VLSI implementation of LDPC decoders.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Design and failure analysis of logic-compatible multilevel gain-cell-based dram for fault-tolerant VLSI systems.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

Random sampling ADC for sparse spectrum sensing.
Proceedings of the 19th European Signal Processing Conference, 2011

Synthesis strategies for sub-VT systems.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

A 772Mbit/s 8.81bit/nJ 90nm CMOS soft-input soft-output sphere decoder.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010
Simulation and Emulation of MIMO Wireless Baseband Transceivers.
EURASIP J. Wireless Comm. and Networking, 2010

MIMO transmission with residual transmit-RF impairments.
Proceedings of the 2010 International ITG Workshop on Smart Antennas, 2010

Area- and throughput-optimized VLSI architecture of sphere decoding.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

VLSI Implementation of Hard- and Soft-Output Sphere Decoding for Wide-Band MIMO Systems.
Proceedings of the VLSI-SoC: Forward-Looking Trends in IC and Systems Design, 2010

Matching pursuit: Evaluation and implementatio for LTE channel estimation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

VLSI implementation of a low-complexity LLL lattice reduction algorithm for MIMO detection.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
Implementation of a 2×2 MIMO-OFDM receiver on an application specific processor.
Microelectronics Journal, 2009

Design and Optimization of an HSDPA Turbo Decoder ASIC.
J. Solid-State Circuits, 2009

2008
Soft-output sphere decoding: algorithms and VLSI implementation.
IEEE Journal on Selected Areas in Communications, 2008

A Real-Time 4-Stream MIMO-OFDM Transceiver: System Design, FPGA Implementation, and Characterization.
IEEE Journal on Selected Areas in Communications, 2008

A 58mW 1.2mm2 HSDPA Turbo Decoder ASIC in 0.13μm CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007
VLSI Implementation of a High-Speed Iterative Sorted MMSE QR Decomposition.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

FFT Processor for OFDM Channel Estimation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

VLSI Implementation of a Lattice-Reduction Algorithm for Multi-Antenna Broadcast Precoding.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Regularized Frequency Domain Equalization Algorithm and its VLSI Implementation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Reduced-complexity mimo detector with close-to ml error rate performance.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Design of spatially multiplexed LDPC codes for multi-user detection.
Proceedings of the 15th European Signal Processing Conference, 2007

2006
K-best MIMO detection VLSI architectures achieving up to 424 Mbps.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Silicon implementation of an MMSE-based soft demapper for MIMO-BICM.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Algorithm and VLSI architecture for linear MMSE detection in MIMO-OFDM systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A Frame-Start Detector for a 4×4 MIMO-OFDM System.
Proceedings of the 2006 IEEE International Conference on Acoustics Speech and Signal Processing, 2006

VLSI implementation of pipelined sphere decoding with early termination.
Proceedings of the 14th European Signal Processing Conference, 2006

Advanced receiver algorithms for MIMO wireless communications.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2004
A 2 Gb/s balanced AES crypto-chip implementation.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

2003
Rapid prototyping for wireless designs: the five-ones approach.
Signal Processing, 2003

Prototype experience for MIMO BLAST over third-generation wireless system.
IEEE Journal on Selected Areas in Communications, 2003

Variable delay ripple carry adder with carry chain interrupt detection.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A 50 Mbps 4×4 maximum likelihood decoder for multiple-input multiple-output systems with QPSK modulation.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003


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