Luca Bettini

Orcid: 0000-0001-5516-8183

According to our database1, Luca Bettini authored at least 13 papers between 2008 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2017
A Fully Integrated Dual-Channel On-Coil CMOS Receiver for Array Coils in 1.5-10.5 T MRI.
IEEE Trans. Biomed. Circuits Syst., 2017

27.4 A sub-1dB NF dual-channel on-coil CMOS receiver for Magnetic Resonance Imaging.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2015
A Reconfigurable 5-to-14 bit SAR ADC for Battery-Powered Medical Instrumentation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A Reconfigurable DT ΔΣ Modulator for Multi-Standard 2G/3G/4G Wireless Receivers.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

Fundamental Power Limits of SAR and ΔΣ Analog-to-Digital Converters.
Proceedings of the Nordic Circuits and Systems Conference, 2015

Integrated CMOS receiver for wearable coil arrays in MRI applications.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
A 1.9 GS/s 4-bit sub-Nyquist flash ADC for 3.8 GHz compressive spectrum sensing in 28 nm CMOS.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

Compressive sensing spectrum recovery from quantized measurements in 28nm SOI CMOS.
Proceedings of the 22nd European Signal Processing Conference, 2014

2013
VLSI Design of a Monolithic Compressive-Sensing Wideband Analog-to-Information Converter.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2013

Digital front-end design for carrier aggregation in next-generation cellular user equipment.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

2011
A 4 Mb LV MOS-Selected Embedded Phase Change Memory in 90 nm Standard CMOS Technology.
IEEE J. Solid State Circuits, 2011

2010
A 90nm 4Mb embedded phase-change memory with 1.2V 12ns read access time and 1MB/s write throughput.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2008
Program circuit for a phase change memory array with 2 MB/s write throughput for embedded applications.
Proceedings of the ESSCIRC 2008, 2008


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