Georgios Karakonstantis
Orcid: 0000-0002-5693-8503
According to our database1,
Georgios Karakonstantis
authored at least 95 papers
between 2007 and 2024.
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Bibliography
2024
Enabling Voltage Over-Scaling in Multiplierless DSP Architectures via Algorithm-Hardware Co-Design.
IEEE Trans. Very Large Scale Integr. Syst., February, 2024
2023
Optimal Adder-Multiplexer Co-Optimization for Time-Multiplexed Multiplierless Architectures.
IEEE Trans. Circuits Syst. I Regul. Pap., September, 2023
ARETE: Accurate Error Assessment via Machine Learning-Guided Dynamic-Timing Analysis.
IEEE Trans. Computers, April, 2023
Estimating Code Vulnerability to Timing Errors Via Microarchitecture-Aware Machine Learning.
IEEE Des. Test, February, 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Proceedings of the 29th International Symposium on On-Line Testing and Robust System Design, 2023
On the Facilitation of Voltage Over-Scaling and Minimization of Timing Errors in Floating-Point Multipliers.
Proceedings of the 29th International Symposium on On-Line Testing and Robust System Design, 2023
A Compressed and Accurate Sparse Deep Learning-based Workload-Aware Timing Error Model.
Proceedings of the 41st IEEE International Conference on Computer Design, 2023
ACOR: On the Design of Energy-Efficient Autocorrelation for Emerging Edge Applications.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
Proceedings of the 30th IEEE Symposium on Computer Arithmetic, 2023
2022
Increased Leverage of Transprecision Computing for Machine Vision Applications at the Edge.
J. Signal Process. Syst., 2022
On the Evaluation of the Total-Cost-of-Ownership Trade-Offs in Edge vs Cloud Deployments: A Wireless-Denial-of-Service Case Study.
IEEE Trans. Sustain. Comput., 2022
IEEE Trans. Parallel Distributed Syst., 2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
Instruction-aware Learning-based Timing Error Models through Significance-driven Approximations.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022
2021
Evaluation of Static Mapping for Dynamic Space-Shared Multi-task Processing on FPGAs.
J. Signal Process. Syst., 2021
Revealing DRAM Operating GuardBands Through Workload-Aware Error Predictive Modeling.
IEEE Trans. Computers, 2021
IEEE Micro, 2021
DTA-PUF: Dynamic Timing-aware Physical Unclonable Function for Resource-constrained Devices.
ACM J. Emerg. Technol. Comput. Syst., 2021
A case study on profiling of an EEG-based brain decoding interface on Cloud and Edge servers.
Proceedings of the 6th IEEE International Conference on Smart Cloud, 2021
Proceedings of the IEEE Workshop on Signal Processing Systems, 2021
Boosting Microprocessor Efficiency: Circuit- and Workload-Aware Assessment of Timing Errors.
Proceedings of the IEEE International Symposium on Workload Characterization, 2021
Fast and Accurate Power Spectral Analysis of Heart Rate Variability using Fast Gaussian Gridding.
Proceedings of the Computing in Cardiology, CinC 2021, Brno, 2021
2020
DStress: Automatic Synthesis of DRAM Reliability Stress Viruses using Genetic Algorithms.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020
DEFCON: Generating and Detecting Failure-prone Instruction Sequences via Stochastic Search.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the 20th IEEE/ACM International Symposium on Cluster, 2020
HaRMony: Heterogeneous-Reliability Memory and QoS-Aware Energy Management on Virtualized Servers.
Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020
2019
Shimmer: Implementing a Heterogeneous-Reliability DRAM Framework on a Commodity Server.
IEEE Comput. Archit. Lett., 2019
Proceedings of the IEEE International Symposium on Workload Characterization, 2019
Optimisation of System Throughput Exploiting Tasks Heterogeneity on Space Shared FPGAs.
Proceedings of the International Conference on Field-Programmable Technology, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Design space exploration of multi-task processing on space shared FPGAs: work-in-progress.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis Companion, 2019
Evaluation of FPGA Partitioning Schemes for Time and Space Sharing of Heterogeneous Tasks.
Proceedings of the Applied Reconfigurable Computing - 15th International Symposium, 2019
2018
Proceedings of the 2018 IEEE SmartWorld, 2018
Characterization of HPC workloads on an ARMv8 based server under relaxed DRAM refresh and thermal stress.
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018
Variation-Aware Pipelined Cores through Path Shaping and Dynamic Cycle Adjustment: Case Study on a Floating-Point Unit.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018
Minimization of Timing Failures in Pipelined Designs via Path Shaping and Operand Truncation.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
DRAM Characterization under Relaxed Refresh Period Considering System Level Effects within a Commodity Server.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
Proceedings of the 24th IEEE International Conference on Parallel and Distributed Systems, 2018
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018
Proceedings of the 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, 2018
An energy-efficient and error-resilient server ecosystem exceeding conservative scaling limits.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Exploring Functional Acceleration of OpenCL on FPGAs and GPUs Through Platform-Independent Optimizations.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018
2017
Dependency-Aware Rollback and Checkpoint-Restart for Distributed Task-Based Runtimes.
CoRR, 2017
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017
Relaxing DRAM refresh rate through access pattern scheduling: A case study on stencil-based algorithms.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017
2016
Cross-Layer Energy-Efficiency Optimization of Packet Based Wireless MIMO Communication Systems.
J. Signal Process. Syst., 2016
IET Comput. Digit. Tech., 2016
Proceedings of the 28th ACM Symposium on Parallelism in Algorithms and Architectures, 2016
A low overhead error confinement method based on application statistical characteristics.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Statistical fault injection for impact-evaluation of timing errors on application performance.
Proceedings of the 53rd Annual Design Automation Conference, 2016
2015
ACM Trans. Embed. Comput. Syst., 2015
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015
Heterogeneous Error-Resilient Scheme for Spectral Analysis in Ultra-Low Power Wearable Electrocardiogram Devices.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Energy versus data integrity trade-offs in embedded high-density logic compatible dynamic memories.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Exploiting dynamic timing margins in microprocessors for frequency-over-scaling with instruction-based clock adjustment.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Mitigating the impact of faults in unreliable memories for error-resilient applications.
Proceedings of the 52nd Annual Design Automation Conference, 2015
The impact of faulty memory bit cells on the decoding of spatially-coupled LDPC codes.
Proceedings of the 49th Asilomar Conference on Signals, Systems and Computers, 2015
2014
Microelectron. J., 2014
Enabling complexity-performance trade-offs for successive cancellation decoding of polar codes.
Proceedings of the 2014 IEEE International Symposium on Information Theory, Honolulu, HI, USA, June 29, 2014
A quality-scalable and energy-efficient approach for spectral analysis of heart rate variability.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014
2013
Exploiting application resiliency for energy-efficient and adequately-reliable operation.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
2012
Logic and Memory Design Based on Unequal Error Protection for Voltage-scalable, Robust and Adaptive DSP Systems.
J. Signal Process. Syst., 2012
Shortening Design Time through Multiplatform Simulations with a Portable OpenCL Golden-model: The LDPC Decoder Case.
Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012
On the exploitation of the inherent error resilience of wireless systems under unreliable silicon.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
Design of energy efficient and dependable health monitoring systems under unreliable nanometer technologies.
Proceedings of the 7th International Conference on Body Area Networks, 2012
Proceedings of the 50th Annual Allerton Conference on Communication, 2012
2011
Containing the Nanometer "Pandora-Box": Cross-Layer Design Techniques for Variation Aware Low Power Systems.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011
Proceedings of the IEEE 29th International Conference on Computer Design, 2011
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011
Proceedings of the 48th Design Automation Conference, 2011
Proceedings of the Low-Power Variation-Tolerant Design in Nanometer Silicon, 2011
2010
Process-Variation Resilient and Voltage-Scalable DCT Architecture for Robust Low-Power Computing.
IEEE Trans. Very Large Scale Integr. Syst., 2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
Low-power DWT-based quasi-averaging algorithm and architecture for epileptic seizure detection.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010
HERQULES: system level cross-layer design exploration for efficient energy-quality trade-offs.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010
A self-consistent model to estimate NBTI degradation and a comprehensive on-line system lifetime enhancement technique.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010
Proceedings of the 28th International Conference on Computer Design, 2010
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
2009
Design Methodology for Low Power and Parametric Robustness Through Output-Quality Modulation: Application to Color-Interpolation Filtering.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
System level DSP synthesis using voltage overscaling, unequal error protection & adaptive quality tuning.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009
Significance driven computation: a voltage-scalable, variation-aware, quality-tuning motion estimator.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009
2007
Low-power process-variation tolerant arithmetic units using input-based elastic clocking.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007
Design methodology to trade off power, output quality and error resiliency: application to color interpolation filtering.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
An Optimal Algorithm for Low Power Multiplierless FIR Filter Design using Chebychev Criterion.
Proceedings of the IEEE International Conference on Acoustics, 2007
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007