Qiuting Huang

According to our database1, Qiuting Huang authored at least 86 papers between 1993 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 2002, "For contributions to integrated circuits for wireless communications".

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2021
Energy-Efficient Hardware-Accelerated Synchronization for Shared-L1-Memory Multiprocessor Clusters.
IEEE Trans. Parallel Distributed Syst., 2021

2020
A 3.3-GHz 101fsrms-Jitter, -250.3dB FOM Fractional-N DPLL with Phase Error Detection Accomplished in Fully Differential Voltage Domain.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

Implementation and performance evaluation of cellular NB-IoT OTDOA positioning.
Proceedings of the IEEE/ION Position, Location and Navigation Symposium, 2020

A Cellular-Modem-Hosted Low-Cost Single-Shot Dual-Mode Assisted-GNSS Receiver for the Internet of Things.
Proceedings of the IEEE/ION Position, Location and Navigation Symposium, 2020

2019
Automatic Resonance Frequency Retuning of Stretchable Liquid Metal Receive Coil for Magnetic Resonance Imaging.
IEEE Trans. Medical Imaging, 2019

Hardware-Accelerated Energy-Efficient Synchronization and Communication for Ultra-Low-Power Tightly Coupled Clusters.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
A Multi-Sensor and Parallel Processing SoC for Miniaturized Medical Instrumentation.
IEEE J. Solid State Circuits, 2018

A 12-bit 300-MS/s SAR ADC With Inverter-Based Preamplifier and Common-Mode-Regulation DAC in 14-nm CMOS FinFET.
IEEE J. Solid State Circuits, 2018

EC-GSM-IoT network synchronization with support for large frequency offsets.
Proceedings of the 2018 IEEE Wireless Communications and Networking Conference, 2018

An 826 MOPS, 210uW/MHz Unum ALU in 65 nm.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A Dual-Mode NB-IoT and EC-GSM RF-SoC Achieving -128-dBm Extended-Coverage and Supporting OTDOA and A-GPS Positioning.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

2017
Optimal Channel Shortener Design for Reduced- State Soft-Output Viterbi Equalizer in Single-Carrier Systems.
IEEE Trans. Commun., 2017

Parallel List Decoding of Convolutional Codes: Algorithm and Implementation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

A Fully Integrated Dual-Channel On-Coil CMOS Receiver for Array Coils in 1.5-10.5 T MRI.
IEEE Trans. Biomed. Circuits Syst., 2017

An 826 MOPS, 210 uW/MHz Unum ALU in 65 nm.
CoRR, 2017

Maximum-Likelihood Detection for Energy-Efficient Timing Acquisition in NB-IoT.
Proceedings of the 2017 IEEE Wireless Communications and Networking Conference Workshops, 2017

A sub-10mW real-time implementation for EMG hand gesture recognition based on a multi-core biomedical SoC.
Proceedings of the 7th IEEE International Workshop on Advances in Sensors and Interfaces, 2017

27.4 A sub-1dB NF dual-channel on-coil CMOS receiver for Magnetic Resonance Imaging.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

A wide tuning-range ADFLL for mW-SoCs with dithering-enhanced accuracy in 65 nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A SAW-less RF-SoC for cellular IoT supporting EC-GSM-IoT -121.7 dBm sensitivity through EGPRS2A 592 kbps throughput.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

A multi-sensor and parallel processing SoC for wearable and implantable telemetry systems.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

Background calibration using noisy reference ADC for a 12 b 600 MS/s 2 × TI SAR ADC in 14nm CMOS FinFET.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

Towards a Mobile Health Platform with Parallel Processing and Multi-sensor Capabilities.
Proceedings of the Euromicro Conference on Digital System Design, 2017

A power-efficient multi-channel PPG ASIC with 112dB receiver DR for pulse oximetry and NIRS.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

Towards an implantable telemetry system for SpO2 and PWV measurement in small animals.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

2016
An output-capacitor-free adaptively biased LDO regulator with robust frequency compensation in 0.13μm CMOS for SoC application.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A low-complexity channel shortening receiver with diversity support for evolved 2G devices.
Proceedings of the 2016 IEEE International Conference on Communications, 2016

A wireless system with stimulation and recording capabilities for interfacing peripheral nerves in rodents.
Proceedings of the 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2016

2015
On the Mapping of Incremental Redundancy into a Physical Layer ASIC.
J. Signal Process. Syst., 2015

A Reconfigurable 5-to-14 bit SAR ADC for Battery-Powered Medical Instrumentation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A Versatile Embedded Platform for EMG Acquisition and Gesture Recognition.
IEEE Trans. Biomed. Circuits Syst., 2015

An Evolved GSM/EDGE Baseband ASIC Supporting Rx Diversity.
IEEE J. Solid State Circuits, 2015

A Reconfigurable DT ΔΣ Modulator for Multi-Standard 2G/3G/4G Wireless Receivers.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

A Low-complexity Channel Shortening Receiver with Diversity Support for Evolved 2G Device.
CoRR, 2015

Channel shortening and equalization based on information rate maximization for evolved GSM/EDGE.
Proceedings of the 2015 IEEE Workshop on Signal Processing Systems, 2015

Integrated CMOS receiver for wearable coil arrays in MRI applications.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Multiple Biopotentials Acquisition System for Wearable Applications.
Proceedings of the BIODEVICES 2015, 2015

An EOG-based, head-mounted eye tracker with 1 kHz sampling rate.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2015

2014
Efficient Parallel Turbo-Decoding for High-Throughput Wireless Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Power-efficient turbo-decoder design based on algorithm-specific power domain partitioning.
Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014

A 1.9 GS/s 4-bit sub-Nyquist flash ADC for 3.8 GHz compressive spectrum sensing in 28 nm CMOS.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

A signal processor for Gaussian message passing.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A novel assisted near-ideal joint decision feedback equalizer for MIMO spatial multiplexing.
Proceedings of the IEEE International Conference on Communication Systems, 2014

Near-optimal joint multiuser detection for MIMO spatial multiplexing TD-HSPA evolution.
Proceedings of the 2014 IEEE/CIC International Conference on Communications in China, 2014

Compressive sensing spectrum recovery from quantized measurements in 28nm SOI CMOS.
Proceedings of the 22nd European Signal Processing Conference, 2014

An evolved EDGE PHY ASIC supporting soft-output equalization and Rx diversity.
Proceedings of the ESSCIRC 2014, 2014

Live demonstration: Modular multi-sensor platform for portable and wireless medical instrumentation.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014

Modular multi-sensor platform for portable and wireless medical instrumentation.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014

EMG-based hand gesture recognition with flexible analog front end.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014

2013
Physical Layer Development Framework for OsmocomBB.
J. Signal Process. Syst., 2013

VLSI Design of a Monolithic Compressive-Sensing Wideband Analog-to-Information Converter.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2013

Digital front-end design for carrier aggregation in next-generation cellular user equipment.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

Efficient vlsi implementation of reduced-state sequence estimation for wireless communications.
Proceedings of the IEEE International Conference on Acoustics, 2013

2012
Implementation Trade-Offs of Soft-Input Soft-Output MAP Decoders for Convolutional Codes.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

Turbo decoder design for high code rates.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

Successive interference cancellation for 3G downlink: Algorithm and VLSI architecture.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

A novel constrained-Viterbi algorithm with linear equalization and grouping assistance.
Proceedings of the 2012 International Symposium on Wireless Communication Systems (ISWCS), 2012

Efficient channel shortening for higher order modulation: Algorithm and architecture.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Low-complexity frequency synchronization for GSM systems: Algorithms and implementation.
Proceedings of the 4th International Congress on Ultra Modern Telecommunications and Control Systems, 2012

2011
Design and Implementation of a Parallel Turbo-Decoder ASIC for 3GPP-LTE.
IEEE J. Solid State Circuits, 2011

A circuit technology platform for medical data acquisition and communication: Outline of a collaboration project within the Swiss Nano-Tera.ch Initiative.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
Design and Optimization of a Digital Baseband Receiver ASIC for GSM/EDGE.
Proceedings of the VLSI-SoC: Forward-Looking Trends in IC and Systems Design, 2010

A 1mm<sup>2</sup> 1.3mW GSM/EDGE digital baseband receiver ASIC in 0.13 µm CMOS.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

A 390Mb/s 3.57mm<sup>2</sup> 3GPP-LTE turbo decoder ASIC in 0.13µm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A tri-band SAW-less WCDMA/HSPA RF CMOS transceiver with on-chip DC-DC converter connectable to battery.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A quad-band class-39 RF CMOS receiver for evolved EDGE.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A 4.5mW digital baseband receiver for level-A evolved EDGE.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A 11.1-bit ENOB 50-MS/s pipelined A/D converter in 130-nm CMOS without S/H front end.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

A 0.13µm CMOS 0.1-20MHz bandwidth 86-70dB DR multi-mode DT ΔΣ ADC for IMT-Advanced.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

2009
Design and Optimization of an HSDPA Turbo Decoder ASIC.
IEEE J. Solid State Circuits, 2009

2008
A 58mW 1.2mm<sup>2</sup> HSDPA Turbo Decoder ASIC in 0.13μm CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007
E2 Digital RF Fundamentally a New Technology or Just Marketing Hype?
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A Linear Uplink WCDMA Modulator with 156dBc/Hz Downlink SNR.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A 50mW HSDPA Baseband Receiver ASIC with Multimode Digital Front-End.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A 0.13μm CMOS EDGE/UMTS/WLAN Tri-Mode ΔΣ ADC with -92dB THD.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2005
A 9.5mW 4GHz WCDMA frequency synthesizer in 0.13µm CMOS.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

1999
90 dB, 90 MHz, 30 mW CMOS OTA for a high capacitive load.
Int. J. Circuit Theory Appl., 1999

1998
On the optimum design of regulated cascode operational transconductance amplifiers.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

1997
Design considerations for high-frequency crystal oscillators digitally trimmable to sub-ppm accuracy.
IEEE Trans. Very Large Scale Integr. Syst., 1997

1996
A 200 µA, 78 MHz CMOS crystal-oscillator digitally trimmable to 0.3 ppm.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

1995
90Db, 90MHz, 30m W OTA with the Gain-Enhancement Implemented by One and Two Stage Amplifiers.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1994
Quantiser Gain in Nth-Order Sigma-Delta Modulator Linear Models: Its Determination Based on Constant Output Power Criterion.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

A Glitch-Free Single-Phase CMOS DFF for Gigahertz Applications.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993
On the Inherent Harmonie Distortion of First-order Sigma-Delta Modulators.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Speed Optimization of Edge-Triggered Nine-Transistor D-Flip-Flops for Gigahertz Single-Phase Clocks.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Linear-phase Filters Configured as a Combination of Sigma-delta Modulator, SC Transversal Filter and a Low-<i>Q</i> Biquad.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993


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