Chun-Chang Lu

According to our database, Chun-Chang Lu authored at least 5 papers between 2009 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

7.7 A 2.16pJ/b 112Gb/s PAM-4 Transceiver with Time-Interleaved 2b/3b ADCs and Unbalanced Baud-Rate CDR for XSR Applications in 28nm CMOS.

Yen-Po Lin, Pen-Jui Peng, Chun-Chang Lu, Po-Ting Shen, Yun-Cheng Jao, Ping-Hsuan Hsieh

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

A 39-Gb/s PAM-3 Transmitter and ADC-Based Receiver Chipset in CMOS Technologies.

Yen-Po Lin, Chun-Chang Lu, Mei-Hsuan Lu, Yueh-Cheng Tsai, Ping-Hsuan Hsieh, Pen-Jui Peng

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024

2015

Three Dimensional Gestures Interface Based on Complex Background for Intelligent Internet Systems.

Yu-Cheng Fan, Chun-Hung Wang, Chun-Chang Lu

Proceedings of the 2015 IEEE International Conference on Systems, 2015

2011

Tunneling component suppression in charge pumping measurement and reliability study for high-k gated MOSFETs.

Chun-Chang Lu, Kuei-Shu Chang-Liao, Chun-Yuan Lu, Shih-Cheng Chang, Tien-Ko Wang, Fu-Chung Hou, Yao-Tung Hsu

Microelectron. Reliab., 2011

2009

Employing vertical dielectric layers to improve the operation performance of flash memory devices.

Chia-Huai Ho, Kuei-Shu Chang-Liao, Chun-Yuan Lu, Chun-Chang Lu, Tien-Ko Wang

Microelectron. Reliab., 2009