Chun-Chang Lu
Orcid: 0009-0001-5398-9137
According to our database1,
Chun-Chang Lu authored at least 8 papers
between 2009 and 2026.
Collaborative distances:
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Bibliography
2026
A Page-Buffer and Fail-Bit Counter-Based In-Memory Computing Platform for 3-D NAND Flash Memory.
IEEE J. Emerg. Sel. Topics Circuits Syst., June, 2026
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2026
A 2.16-pJ/b 112-Gb/s PAM-4 Transceiver With Time-Interleaved 2-b/3-b ADCs and Unbalanced Baud-Rate CDR for XSR Applications in 28-nm CMOS.
IEEE J. Solid State Circuits, February, 2026
2024
7.7 A 2.16pJ/b 112Gb/s PAM-4 Transceiver with Time-Interleaved 2b/3b ADCs and Unbalanced Baud-Rate CDR for XSR Applications in 28nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024
2015
Three Dimensional Gestures Interface Based on Complex Background for Intelligent Internet Systems.
Proceedings of the 2015 IEEE International Conference on Systems, 2015
2011
Tunneling component suppression in charge pumping measurement and reliability study for high-k gated MOSFETs.
Microelectron. Reliab., 2011
2009
Employing vertical dielectric layers to improve the operation performance of flash memory devices.
Microelectron. Reliab., 2009