Po-Ting Shen

Orcid: 0009-0003-2299-734X

According to our database¹, Po-Ting Shen authored at least 2 papers between 2024 and 2026.

Collaborative distances:

Timeline

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2026

A 2.16-pJ/b 112-Gb/s PAM-4 Transceiver With Time-Interleaved 2-b/3-b ADCs and Unbalanced Baud-Rate CDR for XSR Applications in 28-nm CMOS.

[DOI]

IEEE J. Solid State Circuits, February, 2026

2024

7.7 A 2.16pJ/b 112Gb/s PAM-4 Transceiver with Time-Interleaved 2b/3b ADCs and Unbalanced Baud-Rate CDR for XSR Applications in 28nm CMOS.

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2024