Pen-Jui Peng

Orcid: 0000-0001-5736-5746

According to our database1, Pen-Jui Peng authored at least 15 papers between 2013 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2024
7.7 A 2.16pJ/b 112Gb/s PAM-4 Transceiver with Time-Interleaved 2b/3b ADCs and Unbalanced Baud-Rate CDR for XSR Applications in 28nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2022
A 12-14.5-GHz 10.2-mW -249-dB FoM Fractional-N Subsampling PLL With a High-Linearity Phase Interpolator in 40-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2022

A 56-Gb/s PAM-4 Transmitter/Receiver Chipset With Nonlinear FFE for VCSEL-Based Optical Links in 40-nm CMOS.
IEEE J. Solid State Circuits, 2022

Design of ultra-high-speed Transmitters Beyond 100Gb/s in CMOS Technology.
Proceedings of the 2022 International Symposium on VLSI Design, Automation and Test, 2022

2021
A 112-Gb/s PAM-4 Voltage-Mode Transmitter With Four-Tap Two-Step FFE and Automatic Phase Alignment Techniques in 40-nm CMOS.
IEEE J. Solid State Circuits, 2021

A 56-Gb/s PAM-4 Optical Transceiver with Nonlinear FFE for VCSEL Driver in 40nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

2020
6.8 A 100Gb/s NRZ Transmitter with 8-Tap FFE Using a 7b DAC in 40nm CMOS.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019
A 112Gb/s PAM-4 Voltage-Mode Transmitter with 4-Tap Two-Step FFE and Automatic Phase Alignment Techniques in 40nm CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018
A 50-Gb/s Quarter-Rate Voltage-Mode Transmitter with Three-Tap FFE in 40-nm CMOS.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

2017
6.1 A 56Gb/s PAM-4/NRZ transceiver in 40nm CMOS.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2015
A 94 GHz 3D Image Radar Engine With 4TX/4RX Beamforming Scan Technique in 65 nm CMOS Technology.
IEEE J. Solid State Circuits, 2015

Design of 56 Gb/s NRZ and PAM4 SerDes Transceivers in CMOS Technologies.
IEEE J. Solid State Circuits, 2015

CW/FMCW/pulse radar engines for 24/26GHz multi-standard applications in 65nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014
A 94GHz duobinary keying wireless transceiver in 65nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2014

2013
A 94GHz 3D-image radar engine with 4TX/4RX beamforming scan technique in 65nm CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013


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