Ying-Zu Lin

According to our database1, Ying-Zu Lin authored at least 20 papers between 2007 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
An 80MHz-BW 640MS/s Time-Interleaved Passive Noise- Shaping SAR ADC in 22nm FDSOI Process.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

An investigation of group, rater and ratee effects on peer-/self-assessments in a collaborative learning environment in higher education: a cross-classified multilevel analysis.
Proceedings of the 21st International Conference on Advanced Learning Technologies, 2021

2019
A 40MHz-BW 320MS/s Passive Noise-Shaping SAR ADC With Passive Signal-Residue Summation in 14nm FinFET.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2016
A 8.2-mW 10-b 1.6-GS/s 4× TI SAR ADC with fast reference charge neutralization and background timing-skew calibration in 16-nm CMOS.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2015
A 10 bit 320 MS/s Low-Cost SAR ADC for IEEE 802.11ac Applications in 20 nm CMOS.
IEEE J. Solid State Circuits, 2015

2014
A 10b 100kS/s SAR ADC with charge recycling switching method.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2013
Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops.
IEEE Trans. Very Large Scale Integr. Syst., 2013

10-bit 30-MS/s SAR ADC Using a Switchback Switching Method.
IEEE Trans. Very Large Scale Integr. Syst., 2013

A 9-Bit 150-MS/s Subrange ADC Based on SAR Architecture in 90-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

2012
A 1-µW 10-bit 200-kS/s SAR ADC With a Bypass Window for Biomedical Applications.
IEEE J. Solid State Circuits, 2012

A Low-Cost Bit-Error-Rate BIST Circuit for High-Speed ADCs Based on Gray Coding.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

2011
A 0.9-V 11-bit 25-MS/s binary-search SAR ADC in 90-nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010
A 5-bit 3.2-GS/s Flash ADC With a Digital Offset Calibration Scheme.
IEEE Trans. Very Large Scale Integr. Syst., 2010

An Asynchronous Binary-Search ADC Architecture With a Reduced Comparator Count.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure.
IEEE J. Solid State Circuits, 2010

A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009
A 5-bit 4.2-GS/s Flash ADC in 0.13-µm CMOS Process.
IEICE Trans. Electron., 2009

A 5b 800MS/s 2mW asynchronous binary-search ADC in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008
A Digitally Calibrated CMOS Transconductor With a 100-MHz Bandwidth and 75-dB SFDR.
IEEE Trans. Circuits Syst. II Express Briefs, 2008

2007
A 5-bit 4.2-GS/s flash ADC in 0.13-μm CMOS.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007


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