Chun-Gi Lyuh

According to our database1, Chun-Gi Lyuh authored at least 15 papers between 2001 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2022
AIWareK: Compiling PyTorch Model for AI Processor Using MLIR Framework.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

M3FPU: Multiformat Matrix Multiplication FPU Architectures for Neural Network Computations.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

ArtBrain-K: AI Processor based-on 5-PetaFLOPS AI Server System.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

2021
Live Demonstration: A Neural Processor for AI Acceleration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

HPC LINPACK Parameter Optimization on Homo-/Heterogeneous System of ARM Neoverse N1SDP.
Proceedings of the HPC Asia 2021: The International Conference on High Performance Computing in Asia-Pacific Region, 2021

2019
AI 32TFLOPS Autonomous Driving Processor on AI-Ware with Adaptive Power Saving.
Proceedings of the 2019 International SoC Design Conference, 2019

Implementation of Yolo-v2 Image Recognition and Other Testbenches for a CNN Accelerator.
Proceedings of the 9th IEEE International Conference on Consumer Electronics, 2019

Function-Safe Vehicular AI Processor with Nano Core-In-Memory Architecture.
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019

2012
Fast human detection using selective block-based HOG-LBP.
Proceedings of the 19th IEEE International Conference on Image Processing, 2012

2004
Coupling-aware high-level interconnect synthesis [IC layout].
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Memory access scheduling and binding considering energy minimization in multi-bank memory systems.
Proceedings of the 41th Design Automation Conference, 2004

Resource-constrained low-power bus encoding with crosstalk delay elimination.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
High-level synthesis for low power based on network flow method.
IEEE Trans. Very Large Scale Integr. Syst., 2003

2002
Coupling-aware high-level interconnect synthesis for low power.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

2001
An Integrated Data Path Optimization for Low Power Based on Network Flow Method.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001


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