Yong Cheol Peter Cho

According to our database¹, Yong Cheol Peter Cho authored at least 16 papers between 2011 and 2023.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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On csauthors.net:

Bibliography

2023

Chiplet Heterogeneous-Integration AI Processor.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Electronics, Information, and Communication, 2023

2022

M3FPU: Multiformat Matrix Multiplication FPU Architectures for Neural Network Computations.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

ArtBrain-K: AI Processor based-on 5-PetaFLOPS AI Server System.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

2021

Live Demonstration: A Neural Processor for AI Acceleration.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

HPC LINPACK Parameter Optimization on Homo-/Heterogeneous System of ARM Neoverse N1SDP.

[BibT_eX]

[DOI]

Proceedings of the HPC Asia 2021: The International Conference on High Performance Computing in Asia-Pacific Region, 2021

2019

AI 32TFLOPS Autonomous Driving Processor on AI-Ware with Adaptive Power Saving.

[BibT_eX]

[DOI]

Proceedings of the 2019 International SoC Design Conference, 2019

Implementation of Yolo-v2 Image Recognition and Other Testbenches for a CNN Accelerator.

[BibT_eX]

[DOI]

Proceedings of the 9th IEEE International Conference on Consumer Electronics, 2019

Function-Safe Vehicular AI Processor with Nano Core-In-Memory Architecture.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019

2017

A deep learning convolution architecture for simple embedded applications.

[BibT_eX]

[DOI]

Chan Kim

Yong Cheol Peter Cho

Youngsu Kwon

Proceedings of the 7th IEEE International Conference on Consumer Electronics - Berlin, 2017

A 1GHz fault tolerant processor with dynamic lockstep and self-recovering cache for ADAS SoC complying with ISO26262 in automotive electronics.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2014

Accelerating Multiresolution Gabor Feature Extraction for Real Time Vision Applications.

[BibT_eX]

[DOI]

Yong Cheol Peter Cho

Nandhini Chandramoorthy

Kevin M. Irick

Vijaykrishnan Narayanan

J. Signal Process. Syst., 2014

Refresh Enabled Video Analytics (REVA): Implications on power and performance of DRAM supported embedded visual systems.

[BibT_eX]

[DOI]

Siddharth Advani

Nandhini Chandramoorthy

Vijaykrishnan Narayanan

Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

2012

Multiresolution Gabor Feature Extraction for Real Time Applications.

[BibT_eX]

[DOI]

Yong Cheol Peter Cho

Nandhini Chandramoorthy

Kevin M. Irick

Vijaykrishnan Narayanan

Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012

A reconfigurable platform for the design and verification of domain-specific accelerators.

[BibT_eX]

[DOI]

Sungho Park

Yong Cheol Peter Cho

Kevin M. Irick

Vijaykrishnan Narayanan

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

Exploring Gabor Filter Implementations for Visual Cortex Modeling on FPGA.

[BibT_eX]

[DOI]

Vijaykrishnan Narayanan

Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

An FPGA Implementation of Information Theoretic Visual-Saliency System and Its Optimization.

[BibT_eX]

[DOI]

Vijaykrishnan Narayanan

Proceedings of the IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, 2011

Yong Cheol Peter Cho

Timeline

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