Young-Su Kwon

According to our database1, Young-Su Kwon authored at least 25 papers between 1998 and 2010.

Collaborative distances :
  • Dijkstra number2 of five.
  • Erdős number3 of four.



In proceedings 
PhD thesis 




Partial access conflict-relieving programmable address shuffler for parallel memory system in multi-core processor.
Microprocessors and Microsystems - Embedded Hardware Design, 2010

Application-Adaptive Reconfiguration of Memory Address Shuffler for FPGA-Embedded Instruction-Set Processor.
Journal of Circuits, Systems, and Computers, 2010

Transparent session transfer in converged IP Messaging systems.
Proceedings of the 2010 Wireless Telecommunications Symposium, 2010

Implmentation of digital audio effect SoC.
Proceedings of the 2009 IEEE International Conference on Multimedia and Expo, 2009

Partial conflict-relieving programmable address shuffler for parallel memories in multi-core processor.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

Standstill Parameter Identification of Vector-Controlled Induction Motor Using Frequency Characteristics of Rotor Bars.
Proceedings of the Industry Applications Society Annual Meeting, 2008

Application-adaptive reconfiguration of memory address shuffler for FPGA-embedded instruction-set processor.
Proceedings of the FPL 2008, 2008

A 159.2mW SoC implementation of T-DMB receiver including stacked memories.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

Performance-driven event-based synchronization for multi-FPGA simulation accelerator with event time-multiplexing bus.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

A 3-D FPGA wire resource prediction model validated using a 3-D placement and routing tool.
Proceedings of the Seventh International Workshop on System-Level Interconnect Prediction (SLIP 2005), 2005

Simulation acceleration of transaction-level models for SoC with RTL sub-blocks.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Scheduling driven circuit partitioning algorithm for multiple FPGAs using time-multiplexed, off-chip, multi-casting interconnection architecture.
Microprocessors and Microsystems, 2004

Functional Coverage Metric Generation from Temporal Event Relation Graph.
Proceedings of the 2004 Design, 2004

Systematic functional coverage metric synthesis from hierarchical temporal event relation graph.
Proceedings of the 41th Design Automation Conference, 2004

Communication-efficient hardware acceleration for fast functional simulation.
Proceedings of the 41th Design Automation Conference, 2004

Bandwidth tracing arbitration algorithm for mixed-clock SoC with dynamic priority adaptation.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

Signal Scheduling Driven Circuit Partitioning for Multiple FPGAs with Time-multiplexed Interconnection.
Proceedings of the IFIP VLSI-SoC 2003, 2003

SCATOMi: Scheduling Driven Circuit Partitioning Algorithm for Multiple FPGAs using Time-multiplexed, Off-chip, Multicasting Interconnection Architecture.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

MetaCore: an application-specific programmable DSP development system.
IEEE Trans. VLSI Syst., 2000

Pyramid Texture Compression and Decompression Using Interpolative Vector Quantization.
Proceedings of the 2000 International Conference on Image Processing, 2000

Fast development of source-level debugging system using hardware emulation (short paper).
Proceedings of ASP-DAC 2000, 2000

A hardware accelerator for the specular intensity of phong illumination model in 3-dimensional graphics.
Proceedings of ASP-DAC 2000, 2000

DIVA: dual-issue VLIW architecture with media instructions for image processing.
IEEE Trans. Consumer Electronics, 1999

A New Single-Clock Flip-Clop for Half-Swing Clocking.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999