Chun-Po Huang

According to our database, Chun-Po Huang authored at least 15 papers between 2010 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2018

A 12-b 40-MS/s Calibration-Free SAR ADC.

Chung-Wei Hsu, Soon-Jyh Chang, Chun-Po Huang, Li-Jen Chang, Ya-Ting Shyu, Chih-Huei Hou, Hwa-An Tseng, Chih-Yuan Kung, Huan-Jui Hu

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A 11-bit 35-MS/s wide input range SAR ADC in 180-nm CMOS process.

Wen-Chia Luo, Soon-Jyh Chang, Chun-Po Huang, Hao-Sheng Wu

Proceedings of the 2018 International Symposium on VLSI Design, 2018

A Low Energy Consumption 10-Bit 100kS/s SAR ADC with Timing Control Adaptive Window.

Chih-Yuan Kung, Chun-Po Huang, Chia-Chuan Li, Soon-Jyh Chang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017

A 12-bit 40-MS/s calibration-free SAR ADC.

Chung-Wei Hsu, Li-Jen Chang, Chun-Po Huang, Soon-Jyh Chang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016

A Systematic Design Methodology of Asynchronous SAR ADCs.

Chun-Po Huang, Jai-Ming Lin, Ya-Ting Shyu, Soon-Jyh Chang

IEEE Trans. Very Large Scale Integr. Syst., 2016

Analysis of Nonideal Behaviors Based on INL/DNL Plots for SAR ADCs.

Chun-Po Huang, Hsin-Wen Ting, Soon-Jyh Chang

IEEE Trans. Instrum. Meas., 2016

An Efficient and Effective Methodology to Control Turn-On Sequence of Power Switches for Power Gating Designs.

Ya-Ting Shyu, Jai-Ming Lin, Che-Chun Lin, Chun-Po Huang, Soon-Jyh Chang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

A pipeline ADC with latched-based ring amplifiers.

Wen-Tze Chen, Ya-Ting Shyu, Chun-Po Huang, Soon-Jyh Chang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015

A first-order low distortion sigma-delta modulator using split DWA technique and SAR quantizer.

Tien-Feng Hsu, Chun-Po Huang, I-Jen Chao, Soon-Jyh Chang

Proceedings of the VLSI Design, Automation and Test, 2015

2014

Low power pipelined SAR ADC with loading-free architecture.

Jia-Jhang Wu, Soon-Jyh Chang, Sheng-Hsiung Lin, Chun-Po Huang, Guan-Ying Huang

Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

2013

Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops.

Ya-Ting Shyu, Jai-Ming Lin, Chun-Po Huang, Cheng-Wu Lin, Ying-Zu Lin, Soon-Jyh Chang

IEEE Trans. Very Large Scale Integr. Syst., 2013

2012

Mismatch-Aware Common-Centroid Placement for Arbitrary-Ratio Capacitor Arrays Considering Dummy Capacitors.

Cheng-Wu Lin, Jai-Ming Lin, Yen-Chih Chiu, Chun-Po Huang, Soon-Jyh Chang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

A power-efficient sizing methodology of SAR ADCs.

Chun-Po Huang, Soon-Jyh Chang, Guan-Ying Huang, Cheng-Wu Lin

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011

Common-centroid capacitor placement considering systematic and random mismatches in analog integrated circuits.

Cheng-Wu Lin, Jai-Ming Lin, Yen-Chih Chiu, Chun-Po Huang, Soon-Jyh Chang

Proceedings of the 48th Design Automation Conference, 2011

2010

Performance-driven analog placement considering boundary constraint.

Cheng-Wu Lin, Jai-Ming Lin, Chun-Po Huang, Soon-Jyh Chang

Proceedings of the 47th Design Automation Conference, 2010