Jai-Ming Lin

According to our database1, Jai-Ming Lin authored at least 46 papers between 1998 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
Dataflow-Aware Macro Placement Based on Simulated Evolution Algorithm for Mixed-Size Designs.
IEEE Trans. Very Large Scale Integr. Syst., 2021

Thermal-Aware Floorplanning and TSV-Planning for Mixed-Type Modules in a Fixed-Outline 3-D IC.
IEEE Trans. Very Large Scale Integr. Syst., 2021

Thermal-Aware Fixed-Outline Floorplanning Using Analytical Models With Thermal-Force Modulation.
IEEE Trans. Very Large Scale Integr. Syst., 2021

A Fast Power Network Optimization Algorithm for Improving Dynamic IR-drop.
Proceedings of the ISPD '21: International Symposium on Physical Design, 2021

2019
Regularity-Aware Routability-Driven Macro Placement Methodology for Mixed-Size Circuits With Obstacles.
IEEE Trans. Very Large Scale Integr. Syst., 2019

A Novel Macro Placement Approach based on Simulated Evolution Algorithm.
Proceedings of the International Conference on Computer-Aided Design, 2019

Routability-driven Mixed-size Placement Prototyping Approach Considering Design Hierarchy and Indirect Connectivity Between Macros.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
Macro-aware row-style power delivery network design for better routability.
Proceedings of the International Conference on Computer-Aided Design, 2018

A fast thermal-aware fixed-outline floorplanning methodology based on analytical models.
Proceedings of the International Conference on Computer-Aided Design, 2018

Co-synthesis of floorplanning and powerplanning in 3D ICs for multiple supply voltage designs.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

General floorplanning methodology for 3D ICs with an arbitrary bonding style.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Routability-Driven TSV-Aware Floorplanning Methodology for Fixed-Outline 3-D ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Regularity-aware routability-driven placement prototyping algorithm for hierarchical mixed-size circuits.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
A Systematic Design Methodology of Asynchronous SAR ADCs.
IEEE Trans. Very Large Scale Integr. Syst., 2016

An Efficient and Effective Methodology to Control Turn-On Sequence of Power Switches for Power Gating Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

SAINT: handling module folding and alignment in fixed-outline floorplans for 3D ICs.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Placement Density Aware Power Switch Planning Methodology for Power Gating Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Routability-driven floorplanning algorithm for mixed-size modules with fixed-outline constraint.
Proceedings of the VLSI Design, Automation and Test, 2015

2014
F-FM: Fixed-Outline Floorplanning Methodology for Mixed-Size Modules Considering Voltage-Island Constraint.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Current density aware power switch placement algorithm for power gating designs.
Proceedings of the International Symposium on Physical Design, 2014

2013
Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops.
IEEE Trans. Very Large Scale Integr. Syst., 2013

2012
SKB-Tree: A Fixed-Outline Driven Representation for Modern Floorplanning Problems.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Mismatch-Aware Common-Centroid Placement for Arbitrary-Ratio Capacitor Arrays Considering Dummy Capacitors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Routability-driven placement algorithm for analog integrated circuits.
Proceedings of the International Symposium on Physical Design, 2012

Analytical-based approach for capacitor placement with gradient error compensation and device correlation enhancement in analog integrated circuits.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Voltage island-driven floorplanning considering level shifter placement.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
UFO: Unified Convex Optimization Algorithms for Fixed-Outline Floorplanning Considering Pre-Placed Modules.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Common-centroid capacitor placement considering systematic and random mismatches in analog integrated circuits.
Proceedings of the 48th Design Automation Conference, 2011

Efficient multi-layer obstacle-avoiding preferred direction rectilinear Steiner tree construction.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
Performance-driven analog placement considering boundary constraint.
Proceedings of the 47th Design Automation Conference, 2010

UFO: unified convex optimization algorithms for fixed-outline floorplanning.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2005
TCG: A transitive closure graph-based representation for general floorplans.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Placement with symmetry constraints for analog layout design using TCG-S.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
TCG-S: orthogonal coupling of P<sup>*</sup>-admissible representations for general floorplans.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

2003
Corner sequence - a P-admissible floorplan representation with a worst case linear-time packing scheme.
IEEE Trans. Very Large Scale Integr. Syst., 2003

Graph matching-based algorithms for array-based FPGA segmentation design and routing.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Arbitrarily shaped rectilinear module placement using the transitive closure graph representation.
IEEE Trans. Very Large Scale Integr. Syst., 2002

Performance-driven placement for dynamically reconfigurable FPGAs.
ACM Trans. Design Autom. Electr. Syst., 2002

Arbitrary Convex and Concave Rectilinear Module Packing Using TCG.
Proceedings of the 2002 Design, 2002

2001
Generic ILP-based approaches for time-multiplexed FPGA partitioning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Matching-based algorithm for FPGA channel segmentation design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Generic ILP-Based Approaches for Dynamically Reconfigurable FPGA Partitioning.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

An Algorithm for Dynamically Reconfigurable FPGA Placement.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

TCG: A Transitive Closure Graph-Based Representation for Non-Slicing Floorplans.
Proceedings of the 38th Design Automation Conference, 2001

1998
Graph matching-based algorithms for FPGA segmentation design.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998


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