Jai-Ming Lin

According to our database, Jai-Ming Lin authored at least 56 papers between 1998 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Timing-Driven Analytical Placement According to Expected Cell Distribution Range.

Jai-Ming Lin, You-Yu Chang, Wei-Lun Huang

Proceedings of the 2024 International Symposium on Physical Design, 2024

2023

Multilevel Fixed-Outline Component Placement and Graph-Based Ball Assignment for System in Package.

Jai-Ming Lin, Tsung-Lin Tsai, Tsung-Chun Tsai

IEEE Trans. Very Large Scale Integr. Syst., September, 2023

Voltage-Drop Optimization Through Insertion of Extra Stripes to a Power Delivery Network.

Jai-Ming Lin, Yu-Tien Chen, Yang-Tai Kung, Hao-Jia Lin

Proceedings of the 2023 International Symposium on Physical Design, 2023

Routability-Driven Orientation-Aware Analytical Placement for System in Package.

Jai-Ming Lin, Tsung-Chun Tsai, Rui-Ting Shen

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

HyPlace-3D: A Hybrid Placement Approach for 3D ICs Using Space Transformation Technique.

Jai-Ming Lin, Yu-Chien Lin, Hsuan Kung, Wei-Yuan Lin

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

2022

PPOM: An Effective Post-Global Placement Optimization Methodology for Better Wirelength and Routability.

Jai-Ming Lin, Liang-Chi Zane, Min-Chia Tsai, Yung-Chen Chen, Che-Li Lin, Chen-Fa Tsai

IEEE Trans. Very Large Scale Integr. Syst., 2022

A Novel Blockage-Avoiding Macro Placement Approach for 3D ICs Based on POCS.

Jai-Ming Lin, Po-Chen Lu, Heng-Yu Lin, Jia-Ting Tsai

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Routability-Driven Analytical Placement with Precise Penalty Models for Large-Scale 3D ICs.

Jai-Ming Lin, Hao-Yuan Hsieh, Hsuan Kung, Hao-Jia Lin

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

2021

Dataflow-Aware Macro Placement Based on Simulated Evolution Algorithm for Mixed-Size Designs.

Jai-Ming Lin, You-Lun Deng, Ya-Chu Yang, Jia-Jian Chen, Po-Chen Lu

IEEE Trans. Very Large Scale Integr. Syst., 2021

Thermal-Aware Floorplanning and TSV-Planning for Mixed-Type Modules in a Fixed-Outline 3-D IC.

Jai-Ming Lin, Wei-Yi Chang, Hao-Yuan Hsieh, Ya-Ting Shyu, Yeong-Jar Chang, Juin-Ming Lu

IEEE Trans. Very Large Scale Integr. Syst., 2021

Thermal-Aware Fixed-Outline Floorplanning Using Analytical Models With Thermal-Force Modulation.

Jai-Ming Lin, Tai-Ting Chen, Hao-Yuan Hsieh, Ya-Ting Shyu, Yeong-Jar Chang, Juin-Ming Lu

IEEE Trans. Very Large Scale Integr. Syst., 2021

A Fast Power Network Optimization Algorithm for Improving Dynamic IR-drop.

Jai-Ming Lin, Yang-Tai Kung, Zheng-Yu Huang, I-Ru Chen

Proceedings of the ISPD '21: International Symposium on Physical Design, 2021

Routability-driven Global Placer Target on Removing Global and Local Congestion for VLSI Designs.

Jai-Ming Lin, Chung-Wei Huang, Liang-Chi Zane, Min-Chia Tsai, Che-Li Lin, Chen-Fa Tsai

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

DAPA: A Dataflow-Aware Analytical Placement Algorithm for Modern Mixed-Size Circuit Designs.

Jai-Ming Lin, Wei-Fan Huang, Yao-Chieh Chen, Yi-Ting Wang, Po-Wen Wang

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

2019

Regularity-Aware Routability-Driven Macro Placement Methodology for Mixed-Size Circuits With Obstacles.

Jai-Ming Lin, You-Lun Deng, Szu-Ting Li, Bo-Heng Yu, Li-Yen Chang, Te-Wei Peng

IEEE Trans. Very Large Scale Integr. Syst., 2019

A Novel Macro Placement Approach based on Simulated Evolution Algorithm.

Jai-Ming Lin, You-Lun Deng, Ya-Chu Yang, Jia-Jian Chen, Yao-Chieh Chen

Proceedings of the International Conference on Computer-Aided Design, 2019

Routability-driven Mixed-size Placement Prototyping Approach Considering Design Hierarchy and Indirect Connectivity Between Macros.

Jai-Ming Lin, Szu-Ting Li, Yi-Ting Wang

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018

Macro-aware row-style power delivery network design for better routability.

Jai-Ming Lin, Jhih-Sheng Syu, I-Ru Chen

Proceedings of the International Conference on Computer-Aided Design, 2018

A fast thermal-aware fixed-outline floorplanning methodology based on analytical models.

Jai-Ming Lin, Tai-Ting Chen, Yen-Fu Chang, Wei-Yi Chang, Ya-Ting Shyu, Yeong-Jar Chang, Juin-Ming Lu

Proceedings of the International Conference on Computer-Aided Design, 2018

Co-synthesis of floorplanning and powerplanning in 3D ICs for multiple supply voltage designs.

Jai-Ming Lin, Chien-Yu Huang, Jhih-Ying Yang

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

General floorplanning methodology for 3D ICs with an arbitrary bonding style.

Jai-Ming Lin, Chien-Yu Huang

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017

Routability-Driven TSV-Aware Floorplanning Methodology for Fixed-Outline 3-D ICs.

Jai-Ming Lin, Jung-An Yang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Regularity-aware routability-driven placement prototyping algorithm for hierarchical mixed-size circuits.

Jai-Ming Lin, Bo-Heng Yu, Li-Yen Chang

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016

A Systematic Design Methodology of Asynchronous SAR ADCs.

Chun-Po Huang, Jai-Ming Lin, Ya-Ting Shyu, Soon-Jyh Chang

IEEE Trans. Very Large Scale Integr. Syst., 2016

An Efficient and Effective Methodology to Control Turn-On Sequence of Power Switches for Power Gating Designs.

Ya-Ting Shyu, Jai-Ming Lin, Che-Chun Lin, Chun-Po Huang, Soon-Jyh Chang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

SAINT: handling module folding and alignment in fixed-outline floorplans for 3D ICs.

Jai-Ming Lin, Po-Yang Chiu, Yen-Fu Chang

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling.

Liang-Ying Lu, Ching-Yao Chang, Zhao-Hong Chen, Bo-Ting Yeh, Tai-Hua Lu, Peng-Yu Chen, Pin-Hao Tang, Kuen-Jong Lee, Lih-Yih Chiou, Soon-Jyh Chang, Chien-Hung Tsai, Chung-Ho Chen, Jai-Ming Lin

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

Placement Density Aware Power Switch Planning Methodology for Power Gating Designs.

Jai-Ming Lin, Che-Chun Lin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Routability-driven floorplanning algorithm for mixed-size modules with fixed-outline constraint.

Jai-Ming Lin, Chih-Yao Hu, Kai-Chung Chan

Proceedings of the VLSI Design, Automation and Test, 2015

2014

F-FM: Fixed-Outline Floorplanning Methodology for Mixed-Size Modules Considering Voltage-Island Constraint.

Jai-Ming Lin, Ji-Heng Wu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Current density aware power switch placement algorithm for power gating designs.

Jai-Ming Lin, Che-Chun Lin, Zong-Wei Syu, Chih-Chung Tsai, Kevin Huang

Proceedings of the International Symposium on Physical Design, 2014

2013

Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops.

Ya-Ting Shyu, Jai-Ming Lin, Chun-Po Huang, Cheng-Wu Lin, Ying-Zu Lin, Soon-Jyh Chang

IEEE Trans. Very Large Scale Integr. Syst., 2013

2012

SKB-Tree: A Fixed-Outline Driven Representation for Modern Floorplanning Problems.

Jai-Ming Lin, Zhi-Xiong Hung

IEEE Trans. Very Large Scale Integr. Syst., 2012

Mismatch-Aware Common-Centroid Placement for Arbitrary-Ratio Capacitor Arrays Considering Dummy Capacitors.

Cheng-Wu Lin, Jai-Ming Lin, Yen-Chih Chiu, Chun-Po Huang, Soon-Jyh Chang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Routability-driven placement algorithm for analog integrated circuits.

Cheng-Wu Lin, Cheng-Chung Lu, Jai-Ming Lin, Soon-Jyh Chang

Proceedings of the International Symposium on Physical Design, 2012

Analytical-based approach for capacitor placement with gradient error compensation and device correlation enhancement in analog integrated circuits.

Cheng-Wu Lin, Chung-Lin Lee, Jai-Ming Lin, Soon-Jyh Chang

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Voltage island-driven floorplanning considering level shifter placement.

Jai-Ming Lin, Wei-Yi Cheng, Chung-Lin Lee, Richard C. Hsu

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

UFO: Unified Convex Optimization Algorithms for Fixed-Outline Floorplanning Considering Pre-Placed Modules.

Jai-Ming Lin, Zhi-Xiong Hung

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Common-centroid capacitor placement considering systematic and random mismatches in analog integrated circuits.

Cheng-Wu Lin, Jai-Ming Lin, Yen-Chih Chiu, Chun-Po Huang, Soon-Jyh Chang

Proceedings of the 48th Design Automation Conference, 2011

Efficient multi-layer obstacle-avoiding preferred direction rectilinear Steiner tree construction.

Jia-Ru Chuang, Jai-Ming Lin

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010

Performance-driven analog placement considering boundary constraint.

Cheng-Wu Lin, Jai-Ming Lin, Chun-Po Huang, Soon-Jyh Chang

Proceedings of the 47th Design Automation Conference, 2010

UFO: unified convex optimization algorithms for fixed-outline floorplanning.

Jai-Ming Lin, Hsi Hung

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2005

TCG: A transitive closure graph-based representation for general floorplans.

Jai-Ming Lin, Yao-Wen Chang

IEEE Trans. Very Large Scale Integr. Syst., 2005

Placement with symmetry constraints for analog layout design using TCG-S.

Jai-Ming Lin, Guang-Ming Wu, Yao-Wen Chang, Jen-Hui Chuang

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

TCG-S: orthogonal coupling of P^*-admissible representations for general floorplans.

Jai-Ming Lin, Yao-Wen Chang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

2003

Corner sequence - a P-admissible floorplan representation with a worst case linear-time packing scheme.

Jai-Ming Lin, Yao-Wen Chang, Shih-Ping Lin

IEEE Trans. Very Large Scale Integr. Syst., 2003

Graph matching-based algorithms for array-based FPGA segmentation design and routing.

Jai-Ming Lin, Song-Ra Pan, Yao-Wen Chang

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

Arbitrarily shaped rectilinear module placement using the transitive closure graph representation.

Jai-Ming Lin, Hsin-Lung Chen, Yao-Wen Chang

IEEE Trans. Very Large Scale Integr. Syst., 2002

Performance-driven placement for dynamically reconfigurable FPGAs.

Guang-Ming Wu, Jai-Ming Lin, Yao-Wen Chang

ACM Trans. Design Autom. Electr. Syst., 2002

Arbitrary Convex and Concave Rectilinear Module Packing Using TCG.

Jai-Ming Lin, Hsin-Lung Chen, Yao-Wen Chang

Proceedings of the 2002 Design, 2002

2001

Generic ILP-based approaches for time-multiplexed FPGA partitioning.

Guang-Ming Wu, Jai-Ming Lin, Yao-Wen Chang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Matching-based algorithm for FPGA channel segmentation design.

Yao-Wen Chang, Jai-Ming Lin, Martin D. F. Wong

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Generic ILP-Based Approaches for Dynamically Reconfigurable FPGA Partitioning.

Guang-Ming Wu, Jai-Ming Lin, Mango Chia-Tso Chao, Yao-Wen Chang

Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

An Algorithm for Dynamically Reconfigurable FPGA Placement.

Guang-Ming Wu, Jai-Ming Lin, Yao-Wen Chang

Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

TCG: A Transitive Closure Graph-Based Representation for Non-Slicing Floorplans.

Jai-Ming Lin, Yao-Wen Chang

Proceedings of the 38th Design Automation Conference, 2001

1998

Graph matching-based algorithms for FPGA segmentation design.

Yao-Wen Chang, Jai-Ming Lin, D. F. Wong

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998