Claudio Asero

According to our database, Claudio Asero authored at least 4 papers between 2016 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

A 5-nm 60-GS/s 7b 64-Way Time Interleaved Partial Loop Unrolled SAR ADC Achieving 35.2dB SNDR up to 32 GHz.

Claudio Nani, Enrico Monaco, Nicola Ghittori, Alessandro Bosi, Domenico Albano, Claudio Asero, Nicola Codega, Alessio Di Pasquo, Ivan Fabiano, Marco Garampazzi, Fabio Giunco, Leonardo Daniel Herbas Burgos, Gabriele Minoia, Paolo Rossi, Marco Sosio, Leonardo Vignoli, Enrico Temporiti, Shawn Scouten, Stephen Jantzi

IEEE J. Solid State Circuits, April, 2025

An Eight-Lane 800-Gb/s Transceiver for PAM-4 Optical Direct-Detection Applications in 5-nm FinFET Process.

Fabio Giunco, Marco Sosio, Claudio Nani, Ivan Fabiano, Travis Lovitt, Victor Karam, Domenico Albano, Claudio Asero, Nicola Codega, Marco Garampazzi, Nicola Ghittori, Leonardo Daniel Herbas Burgos, Stanley S. K. Ho, Enrico Monaco, Benjamín T. Reyes, Paolo Rossi, Enrico Temporiti, Paolo Pascale, Fernando De Bernardinis, Shawn Scouten, Stephen Jantzi

IEEE J. Solid State Circuits, April, 2025

2024

A 5nm 60GS/s 7b 64-Way Time Interleaved Partial Loop Unrolled SAR ADC Achieving 34dB SNDR up to 32GHz.

Claudio Nani, Enrico Monaco, Nicola Ghittori, Alessandro Bosi, Domenico Albano, Claudio Asero, Nicola Codega, Alessio Di Pasquo, Ivan Fabiano, Marco Garampazzi, Fabio Giunco, Leonardo Daniel Herbas Burgos, Gabriele Minoia, Paolo Rossi, Marco Sosio, Leonardo Vignoli, Enrico Temporiti, Shawn Scouten, Stephen Jantzi

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2016

2.4 A 2-to-16GHz BiCMOS ΔΣ fractional-N PLL synthesizer with integrated VCOs and frequency doubler for wireless backhaul applications.

Tino Copani, Claudio Asero, Matteo Colombo, Paolo Aliberti, Giuseppe Martino, Francesco Clerici

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016