Colin Weltin-Wu
According to our database1,
Colin Weltin-Wu
authored at least 15 papers
between 2008 and 2021.
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Bibliography
2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
2019
Understanding Phase Error and Jitter: Definitions, Implications, Simulations, and Measurement.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
2015
A Linearized Model for the Design of Fractional-N Digital PLLs Based on Dual-Mode Ring Oscillator FDCs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
A 3.5 GHz Digital Fractional-N PLL Frequency Synthesizer Based on Ring Oscillator Frequency-to-Digital Conversion.
IEEE J. Solid State Circuits, 2015
25.1 A highly-digital frequency synthesizer using ring-oscillator frequency-to-digital conversion and noise cancellation.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
2013
An Event-driven Clockless Level-Crossing ADC With Signal-Dependent Adaptive Resolution.
IEEE J. Solid State Circuits, 2013
2012
Event-Driven GHz-Range Continuous-Time Digital Signal Processor With Activity-Dependent Power Dissipation.
IEEE J. Solid State Circuits, 2012
Proceedings of the Symposium on VLSI Circuits, 2012
2011
GHz-range continuous-time programmable digital FIR with power dissipation that automatically adapts to signal activity.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2010
Insights Into Wideband Fractional ADPLLs: Modeling and Calibration of Nonlinearity Induced Fractional Spurs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
A 3.5 GHz Wideband ADPLL With Fractional Spur Suppression Through TDC Dithering and Feedforward Compensation.
IEEE J. Solid State Circuits, 2010
A 3.5GHz wideband ADPLL with fractional spur suppression through TDC dithering and feedforward compensation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
2009
A 3 GHz Fractional All-Digital PLL With a 1.8 MHz Bandwidth Implementing Spur Reduction Techniques.
IEEE J. Solid State Circuits, 2009
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
2008
A 3GHz Fractional-N All-Digital PLL with Precise Time-to-Digital Converter Calibration and Mismatch Correction.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008