Francesco Svelto

According to our database1, Francesco Svelto authored at least 75 papers between 1993 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 2013, "For contributions to analysis and design of radio frequency circuits and systems".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2019
High-Efficiency SiGe-BiCMOS $E$ -Band Power Amplifiers Exploiting Current Clamping in the Common-Base Stage.
IEEE J. Solid State Circuits, 2019

70-90-GHz Self-Tuned Polyphase Filter for Wideband I/Q LO Generation in a 55-nm BiCMOS Transmitter.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

A 26-Gb/s 3-D-Integrated Silicon Photonic Receiver in BiCMOS-55 nm and PIC25G With - 15.2-dBm OMA Sensitivity.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

2018
A PVT-Tolerant >40-dB IRR, 44% Fractional-Bandwidth Ultra-Wideband mm-Wave Quadrature LO Generator for 5G Networks in 55-nm CMOS.
IEEE J. Solid State Circuits, 2018

A K-band low-noise bipolar class-C VCO for 5G backhaul systems in 55 nm BiCMOS technology.
Integr., 2018

A >40dB IRR, 44% fractional-bandwidth ultra-wideband mm-wave quadrature LO generator for 5G networks in 55nm CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

Low phase noise K-band VCO and high efficiency E-band power amplifier for mobile network backhaul in SiGe BiCMOS.
Proceedings of the 2018 International Conference on IC Design & Technology, 2018

2017
Insights Into Phase-Noise Scaling in Switch-Coupled Multi-Core LC VCOs for E-Band Adaptive Modulation Links.
IEEE J. Solid State Circuits, 2017

Design of low-power wideband frequency quadruplers based on transformer-coupled resonators for E-Band backhaul applications.
Integr., 2017

2.6 A SiGe BiCMOS E-band power amplifier with 22% PAE at 18dBm OP1dB and 8.5% at 6dB back-off leveraging current clamping in a common-base stage.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016
Insights Into Silicon Photonics Mach-Zehnder-Based Optical Transmitter Architectures.
IEEE J. Solid State Circuits, 2016

23.4 A 56Gb/s 300mW silicon-photonics transmitter in 3D-integrated PIC25G and 55nm BiCMOS technologies.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

A 25Gb/s 3D-integrated silicon photonics receiver in 65nm CMOS and PIC25G for 100GbE optical links.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A multi-core VCO and a frequency quadrupler for E-Band adaptive-modulation links in 55nm BiCMOS.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

2015
A 40-67 GHz Power Amplifier With 13 dBm ℙ<sub>SAT</sub> and 16% PAE in 28 nm CMOS LP.
IEEE J. Solid State Circuits, 2015

22.9 A 1310nm 3D-integrated silicon photonics Mach-Zehnder-based transmitter with 275mW multistage CMOS driver achieving 6dB extinction ratio at 25Gb/s.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

A 15 GHz-bandwidth 20dBm PSAT power amplifier with 22% PAE in 65nm CMOS.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014
Analysis and Design of a High Voltage Integrated Class-B Amplifier for Ultra-Sound Transducers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

A Low-Noise Design Technique for High-Speed CMOS Optical Receivers.
IEEE J. Solid State Circuits, 2014

A 40-67GHz power amplifier with 13dBm PSAT and 16% PAE in 28 nm CMOS LP.
Proceedings of the ESSCIRC 2014, 2014

A 3D-integrated 25Gbps silicon photonics receiver in PIC25G and 65nm CMOS technologies.
Proceedings of the ESSCIRC 2014, 2014

2013
Analysis and Design of mm-Wave Frequency Dividers Based on Dynamic Latches With Load Modulation.
IEEE J. Solid State Circuits, 2013

A 33.6-to-46.2GHz 32nm CMOS VCO with 177.5dBc/Hz minimum noise FOM using inductor splitting for tuning extension.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

High-voltage integrated Class-B amplifier for ultrasound transducers.
Proceedings of 2013 International Conference on IC Design & Technology, 2013

2012
A 90Vpp 720MHz GBW linear power amplifier for ultrasound imaging transmitters in BCD6-SOI.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A 25Gb/s low noise 65nm CMOS receiver tailored to 100GBASE-LR4.
Proceedings of the 38th European Solid-State Circuit conference, 2012

A 4.8mW inductorless CMOS frequency divider-by-4 with more than 60% fractional bandwidth up to 70GHz.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011
A 24 GHz Subharmonic Direct Conversion Receiver in 65 nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

A Wideband Receiver for Multi-Gbit/s Communications in 65 nm CMOS.
IEEE J. Solid State Circuits, 2011

A Low-Noise Quadrature VCO Based on Magnetically Coupled Resonators and a Wideband Frequency Divider at Millimeter Waves.
IEEE J. Solid State Circuits, 2011

A 6.5mW inductorless CMOS frequency divider-by-4 operating up to 70GHz.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A mm-Wave quadrature VCO based on magnetically coupled resonators.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010
Insights Into Wideband Fractional ADPLLs: Modeling and Calibration of Nonlinearity Induced Fractional Spurs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

A 3.5 GHz Wideband ADPLL With Fractional Spur Suppression Through TDC Dithering and Feedforward Compensation.
IEEE J. Solid State Circuits, 2010

Injection-Locked CMOS Frequency Doublers for μ -Wave and mm-Wave Applications.
IEEE J. Solid State Circuits, 2010

A Low Phase-Noise Multi-Phase LO Generator for Wideband Demodulators Based on Reconfigurable Sub-Harmonic Mixers.
IEEE J. Solid State Circuits, 2010

A 3.5GHz wideband ADPLL with fractional spur suppression through TDC dithering and feedforward compensation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A wideband mm-Wave CMOS receiver for Gb/s communications employing interstage coupled resonators.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A 12Gb/s 39dB loss-recovery unclocked-DFE receiver with bi-dimensional equalization.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A 13.1% tuning range 115GHz frequency generator based on an injection-locked frequency doubler in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009
Design of Low-Loss Transmission Lines in Scaled CMOS by Accurate Electromagnetic Simulations.
IEEE J. Solid State Circuits, 2009

A 3 GHz Fractional All-Digital PLL With a 1.8 MHz Bandwidth Implementing Spur Reduction Techniques.
IEEE J. Solid State Circuits, 2009

A Multi-Standard 1.5 to 10 Gb/s Latch-Based 3-Tap DFE Receiver With a SSC Tolerant CDR for Serial Backplane Communication.
IEEE J. Solid State Circuits, 2009

A reconfigurable demodulator with 3-to-5GHz agile synthesizer for 9-band WiMedia UWB in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

Insights into wideband fractional All-Digital PLLs for RF applications.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

A 5.2mW ku-band CMOS injection-locked frequency doubler with differential input / output.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

A sliding IF receiver for mm-wave WLANs in 65nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008
A 30.5 dBm 48% PAE CMOS Class-E PA With Integrated Balun for RF Applications.
IEEE J. Solid State Circuits, 2008

A 3GHz Fractional-N All-Digital PLL with Precise Time-to-Digital Converter Calibration and Mismatch Correction.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

A 24GHz Sub-Harmonic Receiver Front-End with Integrated Multi-Phase LO Generation in 65nm CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

Architectures and Circuit Techniques for Nanoscale RF CMOS (Forum).
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

A 10Gb/s receiver with linear backplane equalization and mixer-based self-aligned CDR.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
CMOS balanced regenerative frequency dividers for wide-band quadrature LO generation.
Microelectron. J., 2007

A 20 mW 3.24mm<sup>2</sup> Fully Integrated GPS Radio for Location Based Services.
IEEE J. Solid State Circuits, 2007

A Magnetically Tuned Quadrature Oscillator.
IEEE J. Solid State Circuits, 2007

A 750 mV Fully Integrated Direct Conversion Receiver Front-End for GSM in 90-nm CMOS.
IEEE J. Solid State Circuits, 2007

A 3.2-to-7.3GHz Quadrature Oscillator with Magnetic Tuning.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A 1.7-GHz 31dBm differential CMOS Class-E Power Amplifier with 58% PAE.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
A 1.8-GHz injection-locked quadrature CMOS VCO with low phase noise and high phase accuracy.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006

CMOS injection locked oscillators for quadrature generation at radio-frequency.
Microelectron. J., 2006

A 20mw 3.24mm2 fully integrated gps radio for cell-phones.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

A 750mV 15kHz 1/f Noise Corner 51dBm IIP2 Direct-Conversion Front-End for GSM in 90nm CMOS.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005
Statistical analysis of second-order intermodulation distortion in WCDMA direct conversion receivers.
IEEE Trans. Circuits Syst. II Express Briefs, 2005

Hybrid cascode compensation for two-stage CMOS operational amplifiers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Balanced CMOS LC-tank analog frequency dividers for quadrature LO generation.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

An interference robust 0.18μm CMOS 3.1-8GHz receiver front-end for UWB radio.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004
Analysis and design of a dual band reconfigurable VCO.
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

Design space exploration for a UMTS front-end exploiting analog platforms.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

2001
Implementation of a CMOS LNA plus mixer for GPS applications with no external components.
IEEE Trans. Very Large Scale Integr. Syst., 2001

2000
An 8mA, 3.8dB NF, 40dB gain CMOS front-end for GPS applications.
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

Solutions for image rejection CMOS LNA.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999
A low-voltage topology for CMOS RF mixers.
IEEE Trans. Consumer Electron., 1999

1998
Very accurate high-frequency noise spectral analysis of P-channel FET's.
IEEE Trans. Instrum. Meas., 1998

Measurement and modeling of Si integrated inductors.
IEEE Trans. Instrum. Meas., 1998

1993
A BiCMOS Tunable Shaper for Detectors of Elementary Particles.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993


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