Daniele Baldi
According to our database1,
Daniele Baldi
authored at least 17 papers
between 2008 and 2020.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2020
12.2 A 4-Channel 200Gb/s PAM-4 BiCMOS Transceiver with Silicon Photonics Front-Ends for Gigabit Ethernet Applications.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2016
Insights Into Silicon Photonics Mach-Zehnder-Based Optical Transmitter Architectures.
IEEE J. Solid State Circuits, 2016
23.4 A 56Gb/s 300mW silicon-photonics transmitter in 3D-integrated PIC25G and 55nm BiCMOS technologies.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
A 25Gb/s 3D-integrated silicon photonics receiver in 65nm CMOS and PIC25G for 100GbE optical links.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
22.9 A 1310nm 3D-integrated silicon photonics Mach-Zehnder-based transmitter with 275mW multistage CMOS driver achieving 6dB extinction ratio at 25Gb/s.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
2014
IEEE J. Solid State Circuits, 2014
A 3D-integrated 25Gbps silicon photonics receiver in PIC25G and 65nm CMOS technologies.
Proceedings of the ESSCIRC 2014, 2014
A 5<sup>th</sup> order gm-C low-pass filter with ±3% cut-off frequency accuracy and 220MHz to 3.3GHz tuning-range in 28nm LP CMOS.
Proceedings of the ESSCIRC 2014, 2014
2012
Proceedings of the 38th European Solid-State Circuit conference, 2012
2010
Insights Into Wideband Fractional ADPLLs: Modeling and Calibration of Nonlinearity Induced Fractional Spurs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
A 3.5 GHz Wideband ADPLL With Fractional Spur Suppression Through TDC Dithering and Feedforward Compensation.
IEEE J. Solid State Circuits, 2010
A 3.5GHz wideband ADPLL with fractional spur suppression through TDC dithering and feedforward compensation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
2009
A 3 GHz Fractional All-Digital PLL With a 1.8 MHz Bandwidth Implementing Spur Reduction Techniques.
IEEE J. Solid State Circuits, 2009
A Multi-Standard 1.5 to 10 Gb/s Latch-Based 3-Tap DFE Receiver With a SSC Tolerant CDR for Serial Backplane Communication.
IEEE J. Solid State Circuits, 2009
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
2008
A 3GHz Fractional-N All-Digital PLL with Precise Time-to-Digital Converter Calibration and Mismatch Correction.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008