Constantine D. Polychronopoulos

According to our database1, Constantine D. Polychronopoulos
  • authored at least 104 papers between 1986 and 2012.
  • has a "Dijkstra number"2 of three.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2012
Efficient real-time similarity detection for video caching and streaming.
Proceedings of the 19th IEEE International Conference on Image Processing, 2012

2010
On the efficacy of call graph-level thread-level speculation.
Proceedings of the first joint WOSP/SIPEW International Conference on Performance Engineering, 2010

Exploitation of nested thread-level speculative parallelism on multi-core systems.
Proceedings of the 7th Conference on Computing Frontiers, 2010

2009
Cache-aware partitioning of multi-dimensional iteration spaces.
Proceedings of of SYSTOR 2009: The Israeli Experimental Systems Conference 2009, 2009

Efficient Scheduling of Nested Parallel Loops on Multi-Core Systems.
Proceedings of the ICPP 2009, 2009

2008
Cache-aware iteration space partitioning.
Proceedings of the 13th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2008

2007
A Cross-Layer Analysis of Session Setup Delay in IP Multimedia Subsystem (IMS) With EV-DO Wireless Transmission.
IEEE Trans. Multimedia, 2007

Tight analysis of the performance potential of thread speculation using spec CPU 2006.
Proceedings of the 12th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2007

2006
A general approach for partitioning N-dimensional parallel nested loops with conditionals.
Proceedings of the SPAA 2006: Proceedings of the 18th Annual ACM Symposium on Parallelism in Algorithms and Architectures, Cambridge, Massachusetts, USA, July 30, 2006

Automatic Granularity Selection and OpenMP Directive Generation Via Extended Machine Descriptors in the PROMIS Parallelizing Compiler.
Proceedings of the OpenMP Shared Memory Parallel Programming - International Workshops, 2006

On the performance potential of different types of speculative thread-level parallelism: The DL version of this paper includes corrections that were not made available in the printed proceedings.
Proceedings of the 20th Annual International Conference on Supercomputing, 2006

Lightweight lock-free synchronization methods for multithreading.
Proceedings of the 20th Annual International Conference on Supercomputing, 2006

History-aware Self-Scheduling.
Proceedings of the 2006 International Conference on Parallel Processing (ICPP 2006), 2006

Probablistic Self-Scheduling.
Proceedings of the Euro-Par 2006, Parallel Processing, 12th International Euro-Par Conference, Dresden, Germany, August 28, 2006

2005
Computational network federations: a middleware architecture for network-based computing.
IEEE Journal on Selected Areas in Communications, 2005

A novel approach for partitioning iteration spaces with variable densities.
Proceedings of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2005

Hardware Support for Multithreaded Execution of Loops with Limited Parallelism.
Proceedings of the Advances in Informatics, 2005

An Efficient Approach for Self-scheduling Parallel Loops on Multiprogrammed Parallel Computers.
Proceedings of the Languages and Compilers for Parallel Computing, 2005

Enhanced Loop Coalescing: A Compiler Technique for Transforming Non-uniform Iteration Spaces.
Proceedings of the High-Performance Computing - 6th International Symposium, 2005

Computational network federations: computing & communications as a utility.
Proceedings of the International Conference on Pervasive Services 2005, 2005

Computational Federation Service: Dynamic Resource Virtualization for Extensible Grid Service Design.
Proceedings of the Joint International Conference on Autonomic and Autonomous Systems 2005 / International Conference on Networking and Services 2005, 2005

2004
A Framework for Incremental Extensible Compiler Construction.
International Journal of Parallel Programming, 2004

Loop Scheduling for Multithreaded Processors.
Proceedings of the 2004 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004), 2004

A Geometric Approach for Partitioning N-Dimensional Non-rectangular Iteration Spaces.
Proceedings of the Languages and Compilers for High Performance Computing, 2004

2003
Adaptive scheduling under memory constraints on non-dedicated computationalfarms.
Future Generation Comp. Syst., 2003

Java Virtual Machine support for object serialization.
Concurrency and Computation: Practice and Experience, 2003

A framework for incremental extensible compiler construction.
Proceedings of the 17th Annual International Conference on Supercomputing, 2003

2002
Scheduler-Activated Dynamic Page Migration for Multiprogrammed DSM Multiprocessors.
J. Parallel Distrib. Comput., 2002

Runtime vs. Manual Data Distribution for Architecture-Agnostic Shared-Memory Programming Models.
International Journal of Parallel Programming, 2002

Overview: An Integrated Framework for Performance Engineering and Resource-Aware Compilation.
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002

Adaptive Scheduling under Memory Pressure on Multiprogrammed SMPs.
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002

Effective Cross-Platform, Multilevel Parallelism via Dynamic Adaptive Execution.
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002

Adaptive Scheduling under Memory Pressure on Multiprogrammed Cluster.
Proceedings of the 2nd IEEE International Symposium on Cluster Computing and the Grid (CCGrid 2002), 2002

2001
Scaling irregular parallel codes with minimal programming effort.
Proceedings of the 2001 ACM/IEEE conference on Supercomputing, 2001

Optimizing Compiler Design for Modularity and Extensibility.
Proceedings of the Languages and Compilers for Parallel Computing, 2001

Java virtual machine support for object serialization.
Proceedings of the ACM 2001 Java Grande Conference, Stanford University, California, USA, 2001

NanoProtean: Scalable System Software for a Gigabit Active Router.
Proceedings of the Proceedings IEEE INFOCOM 2001, 2001

alpha-coral: a multigrain, multithreaded processor architecture.
Proceedings of the 15th international conference on Supercomputing, 2001

The trade-off between implicit and explicit data distribution in shared-memory programming paradigms.
Proceedings of the 15th international conference on Supercomputing, 2001

Improving Java Server Performance with Interruptlets.
Proceedings of the Computational Science - ICCS 2001, 2001

2000
Architectural and compiler techniques for energy reduction in high-performance microprocessors.
IEEE Trans. VLSI Syst., 2000

Using dynamic cache management techniques to reduce energy in general purpose processors.
IEEE Trans. VLSI Syst., 2000

The Design of the PROMIS Compiler-Towards Multi-Level Parallelization.
International Journal of Parallel Programming, 2000

Is Data Distribution Necessary in OpenMP?
Proceedings of the Proceedings Supercomputing 2000, 2000

UPMLIB: A Runtime System for Tuning the Memory Performance of OpenMP Programs on Scalable Shared-Memory Multiprocessors.
Proceedings of the Languages, 2000

Leveraging Transparent Data Distribution in OpenMP via User-Level Dynamic Page Migration.
Proceedings of the High Performance Computing, Third International Symposium, 2000

A case for use-level dynamic page migration.
Proceedings of the 14th international conference on Supercomputing, 2000

User-Level Dynamic Page Migration for Multiprogrammed Shared-Memory Multiprocessors.
Proceedings of the 2000 International Conference on Parallel Processing, 2000

1999
Estimating minimum parallel execution time of loops with loop-carried dependencies.
Systems and Computers in Japan, 1999

Symbolic Analysis in the PROMIS Compiler.
Proceedings of the Languages and Compilers for Parallel Computing, 1999

Using dynamic cache management techniques to reduce energy in a high-performance processor.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

Multithreading Runtime Support for Loop and Functional Parallelism.
Proceedings of the High Performance Computing, Second International Symposium, 1999

An analytical, transistor-level energy model for SRAM-based caches.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Energy and Performance Improvements in Microprocessor Design Using a Loop Cache.
Proceedings of the IEEE International Conference On Computer Design, 1999

The Design of the PROMIS Compiler.
Proceedings of the Compiler Construction, 8th International Conference, 1999

The Modulo Interval: A Simple and Practical Representation for Program Analysis.
Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques, 1999

1998
Architectural and compiler support for energy reduction in the memory hierarchy of high performance microprocessors.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

Retrospective: The Cedar System.
Proceedings of the 25 Years of the International Symposia on Computer Architecture (Selected Papers)., 1998

1997
Practical Parallelization of a Molecular Dynamics Application on Shared and Distributed Memory Machines.
Proceedings of the Eighth SIAM Conference on Parallel Processing for Scientific Computing, 1997

Achieving Multi-level Parallelization.
Proceedings of the High Performance Computing, International Symposium, 1997

The PROMIS Compiler Prototype.
Proceedings of the 1997 Conference on Parallel Architectures and Compilation Techniques (PACT '97), 1997

1996
Symbolic Analysis for Parallelizing Compilers.
ACM Trans. Program. Lang. Syst., 1996

sigma-SSA and Its Construction Through Symbolic Interpretation.
Proceedings of the Languages and Compilers for Parallel Computing, 1996

Estimating Minimum Execution Time of Perfect Loop Nests with Loop-Carried Dependences.
Proceedings of the Languages and Compilers for Parallel Computing, 1996

Estimating Parallel Execution Time of Loops with Loop-Carried Dependencies.
Proceedings of the 1996 International Conference on Parallel Processing, 1996

1995
Extracting Task-Level Parallelism
ACM Trans. Program. Lang. Syst., 1995

The Synergetic Effect of Compiler, Architecture, and Manual Optimizations on the Performance of CFD On Multiprocessors.
Proceedings of the Proceedings Supercomputing '95, San Diego, CA, USA, December 4-8, 1995, 1995

The Performance Impact of Granularity Control and Functional Parallelism.
Proceedings of the Languages and Compilers for Parallel Computing, 1995

1994
The hierarchical task graph as a universal intermediate representation.
International Journal of Parallel Programming, 1994

The Data Partitioning Graph: Extending Data and Control Dependencies for Data Partitioning.
Proceedings of the Languages and Compilers for Parallel Computing, 1994

Autoscheduling in a Distributed Shared-Memory Environment.
Proceedings of the Languages and Compilers for Parallel Computing, 1994

1993
Parallel Programming Issues.
International Journal of High Speed Computing, 1993


Symbolic Analysis: A Basis for Parallelization, Optimization, and Scheduling of Programs.
Proceedings of the Languages and Compilers for Parallel Computing, 1993

1992
Automatic Extraction of Functional Parallelism from Ordinary Programs.
IEEE Trans. Parallel Distrib. Syst., 1992

Microarchitecture support for dynamic scheduling of acyclic task graphs.
Proceedings of the 25th Annual International Symposium on Microarchitecture, 1992

Symbolic Program Analysis and Optimization for Parallelizing Compilers.
Proceedings of the Languages and Compilers for Parallel Computing, 1992

1991
An Analytical Approach to Performance/Cost Modeling of Parallel Computers.
J. Parallel Distrib. Comput., 1991

Optimization of Data/Control Conditions in Task Graphs.
Proceedings of the Languages and Compilers for Parallel Computing, 1991

Run-Time Management of Lisp Parallelism and the Hierarchical Task Graph Program Representation.
Proceedings of the Languages and Compilers for Parallel Computing, 1991

The hierarchical task graph and its use in auto-scheduling.
Proceedings of the 5th international conference on Supercomputing, 1991

Broadcast Networks for Fast Synchronization.
Proceedings of the International Conference on Parallel Processing, 1991

1990
Fast barrier synchronization hardware.
Proceedings of the Proceedings Supercomputing '90, New York, NY, USA, November 12-16, 1990, 1990

1989
Utilizing Multidimensional Loop Parallelism on Large-Scale Parallel Processor Systems.
IEEE Trans. Computers, 1989

Parafrase-2: an Environment for Parallelizing, Partitioning, Synchronizing, and Scheduling Programs on Multiprocessors.
International Journal of High Speed Computing, 1989

Efficient circuit partitioning algorithms for parallel logic simulation.
Proceedings of the Proceedings Supercomputing '89, Reno, NV, USA, November 12-17, 1989, 1989

An efficient message-passing scheduler based on guided self scheduling.
Proceedings of the 3rd international conference on Supercomputing, 1989

Parafrase-2: An Environment for Parallelizing Partitioning Synchronizing and Scheduling Programs on Multiprocessors.
Proceedings of the International Conference on Parallel Processing, 1989

Multiprocessing versus Multiprogramming.
Proceedings of the International Conference on Parallel Processing, 1989

The Effect of Barrier Synchronization and Scheduling Overhead on Parallel Loops.
Proceedings of the International Conference on Parallel Processing, 1989

1988
Toward auto-scheduling compilers.
The Journal of Supercomputing, 1988

Compiler Optimizations for Enhancing Parallelism and Their Impact on Architecture Design.
IEEE Trans. Computers, 1988

Special Issue on Languages, Compilers and Environments for Parallel Programming.
J. Parallel Distrib. Comput., 1988

Compiling issues for supercomputers.
Proceedings of the Proceedings Supercomputing '88, Orlando, FL, USA, November 12-17, 1988, 1988

Partitioning programs for parallel execution.
Proceedings of the 2nd international conference on Supercomputing, 1988

The Impact of Run-Time Overhead on Usable Parallelism.
Proceedings of the International Conference on Parallel Processing, 1988

1987
Guided Self-Scheduling: A Practical Scheduling Scheme for Parallel Supercomputers.
IEEE Trans. Computers, 1987

Processor Allocation for Horizontal and Vertical Parallelism and Related Speedup Bounds.
IEEE Trans. Computers, 1987

On the combination of hardware and software concurrency extraction methods.
Proceedings of the 20st Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1987

Advanced Loop Optimizations for Parallel Computers.
Proceedings of the Supercomputing, 1987

Loop Coalesing: A Compiler Transformation for Parallel Machines.
Proceedings of the International Conference on Parallel Processing, 1987

Automatic Restructuring of Fortran Programs for Parallel Execution.
Proceedings of the Parallel Computing in Science and Engineering, 1987

1986
Execution of Parallel Loops on Parallel Processor Systems.
Proceedings of the International Conference on Parallel Processing, 1986

Speedup Bounds and Processor Allocation for Parallel Programs on Multiprocessors.
Proceedings of the International Conference on Parallel Processing, 1986


  Loading...