Srinivas Patil

According to our database, Srinivas Patil authored at least 28 papers between 1989 and 2012.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2012

Functional Test-Sequence Grading at Register-Transfer Level.

Hongxia Fang, Krishnendu Chakrabarty, Abhijit Jas, Srinivas Patil, Chandra Tirumurti

IEEE Trans. Very Large Scale Integr. Syst., 2012

Test generation for clock-domain crossing faults in integrated circuits.

Naghmeh Karimi, Krishnendu Chakrabarty, Pallav Gupta, Srinivas Patil

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011

Testing of Clock-Domain Crossing Faults in Multi-core System-on-Chip.

Naghmeh Karimi, Zhiqiu Kong, Krishnendu Chakrabarty, Pallav Gupta, Srinivas Patil

Proceedings of the 20th IEEE Asian Test Symposium, 2011

2009

FPGA-based hardware acceleration for Boolean satisfiability.

Kanupriya Gulati, Suganth Paul, Sunil P. Khatri, Srinivas Patil, Abhijit Jas

ACM Trans. Design Autom. Electr. Syst., 2009

The Challenges of Nanotechnology and Gigacomplexity.

Gadi Singer, Rajesh Galivanche, Srinivas Patil, Mike Tripp

IEEE Des. Test Comput., 2009

RT-Level Deviation-Based Grading of Functional Test Sequences.

Hongxia Fang, Krishnendu Chakrabarty, Abhijit Jas, Srinivas Patil, Chandra Tirumurti

Proceedings of the 27th IEEE VLSI Test Symposium, 2009

2008

A low-cost concurrent error detection technique for processor control logic.

Ramtilak Vemu, Abhijit Jas, Jacob A. Abraham, Srinivas Patil, Rajesh Galivanche

Proceedings of the Design, Automation and Test in Europe, 2008

2007

Analysis of Specified Bit Handling Capability of Combinational Expander Networks.

Abhijit Jas, Srinivas Patil

Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

Estimating the Fault Coverage of Functional Test Sequences Without Fault Simulation.

Irith Pomeranz, Praveen Parvathala, Srinivas Patil

Proceedings of the 16th Asian Test Symposium, 2007

The Region-Exhaustive Fault Model.

Abhijit Jas, Suriyaprakash Natarajan, Srinivas Patil

Proceedings of the 16th Asian Test Symposium, 2007

2006

Path Delay Fault Simulation on Large Industrial Designs.

Suriyaprakash Natarajan, Srinivas Patil, Sreejit Chakravarty

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

A Functional Coverage Metric for Estimating the Gate-Level Fault Coverage of Functional Tests.

Sungchul Park, Li Chen, Praveen Parvathala, Srinivas Patil, Irith Pomeranz

Proceedings of the 2006 IEEE International Test Conference, 2006

Selecting High-Quality Delay Tests for Manufacturing Test and Debug.

Hangkyu Lee, Suriyaprakash Natarajan, Srinivas Patil, Irith Pomeranz

Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

A Functional Fault Model with Implicit Fault Effect Propagation Requirements.

Irith Pomeranz, Srinivas Patil, Praveen Parvathala

Proceedings of the 15th Asian Test Symposium, 2006

2005

Compressing Functional Tests for Microprocessors.

Kedarnath J. Balakrishnan, Nur A. Touba, Srinivas Patil

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

1996

A weighted random pattern test generation system.

Rohit Kapur, Srinivas Patil, Thomas J. Snethen, Thomas W. Williams

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

1994

On broad-side delay test.

Jacob Savir, Srinivas Patil

IEEE Trans. Very Large Scale Integr. Syst., 1994

Design of an Efficient Weighted-Random-Pattern Generation System.

Rohit Kapur, Srinivas Patil, Thomas J. Snethen, Thomas W. Williams

Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

1993

Scan-based transition test.

Jacob Savir, Srinivas Patil

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

1992

Skewed-Load Transition Test: Part 2, Coverage.

Srinivas Patil, Jacob Savir

Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

1991

Parallel algorithms for test generation and fault simulation

Srinivas Patil

PhD thesis, 1991

Performance trade-offs in a parallel test generation/fault simulation environment.

Srinivas Patil, Prithviraj Banerjee

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

A Layout Driven Design for Testability Technique for MOS VLSI Circuits.

Sungho Kim, Prithviraj Banerjee, Srinivas Patil

Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

Parallel Test Generation for Sequential Circuits on General-Purpose Multiprocessors.

Srinivas Patil, Prithviraj Banerjee, Janak H. Patel

Proceedings of the 28th Design Automation Conference, 1991

1990

A parallel branch and bound algorithm for test generation.

Srinivas Patil, Prithviraj Banerjee

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

1989

Efficient circuit partitioning algorithms for parallel logic simulation.

Srinivas Patil, Prithviraj Banerjee, Constantine D. Polychronopoulos

Proceedings of the Proceedings Supercomputing '89, Reno, NV, USA, November 12-17, 1989, 1989

Fault Partitioning Issues in an Integrated Parallel Test Generation/Fault Simulation Environment.

Srinivas Patil, Prithviraj Banerjee

Proceedings of the Proceedings International Test Conference 1989, 1989

A test generation system for path delay faults.

Srinivas Patil, Sudhakar M. Reddy

Proceedings of the Computer Design: VLSI in Computers and Processors, 1989