Daihan Wang

According to our database, Daihan Wang authored at least 8 papers between 2006 and 2011.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2011

A Dynamic Link-Width Optimization for Network-on-Chip.

Daihan Wang, Michihiro Koibuchi, Tomohiro Yoneda, Hiroki Matsutani, Hideharu Amano

Proceedings of the 17th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2011

2009

A Link Removal Methodology for Application-Specific Networks-on-Chip on FPGAs.

Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano

IEICE Trans. Inf. Syst., 2009

2008

Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks.

Hiroki Matsutani, Michihiro Koibuchi, Daihan Wang, Hideharu Amano

Proceedings of the Second International Symposium on Networks-on-Chips, 2008

A link removal methodology for Networks-on-Chip on reconfigurable systems.

Daihan Wang, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi

Proceedings of the FPL 2008, 2008

Run-time power gating of on-chip routers using look-ahead routing.

Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Daihan Wang

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007

A Port Combination Methodology for Application-Specific Networks-on-Chip on FPGAs.

Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano

IEICE Trans. Inf. Syst., 2007

A Temporal Correlation Based Port Combination Methodology for Networks-on-chip on Reconfigurable Systems.

Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano

Proceedings of the FPL 2007, 2007

2006

A Parametric Study of Scalable Interconnects on FPGAs.

Daihan Wang, Hiroki Matsutani, Masato Yoshimi, Michihiro Koibuchi, Hideharu Amano

Proceedings of the 2006 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2006