Hideharu Amano

According to our database1, Hideharu Amano authored at least 415 papers between 1983 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of two.

Timeline

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Bibliography

2019
Designing High-Performance Interconnection Networks with Host-Switch Graphs.
IEEE Trans. Parallel Distrib. Syst., 2019

A Fine-Grained Multicasting of Configuration Data for Coarse-Grained Reconfigurable Architectures.
IEICE Transactions, 2019

Extracting Success from IBM's 20-Qubit Machines Using Error-Aware Compilation.
CoRR, 2019

The Evaluation of Partial Reconfiguration for a Multi-board FPGA System FiCSW.
Proceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, 2019

Acceleration of Deep Recurrent Neural Networks with an FPGA cluster.
Proceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, 2019

An ARM-based heterogeneous FPGA accelerator for Hall thruster simulation.
Proceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, 2019

Sparse 3-D NoCs with Inductive Coupling.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Implementing a large application(LSTM) on the multi-FPGA system: Flow-in-Cloud.
Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2019

Key-value Store Chip Design for Low Power Consumption.
Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2019

2018
Asymmetric Body Bias Control With Low-Power FD-SOI Technologies: Modeling and Power Optimization.
IEEE Trans. VLSI Syst., 2018

Body Bias Control for Renewable Energy Source with a High Inner Resistance.
IEEE Trans. Multi-Scale Computing Systems, 2018

Digitally Assisted On-Chip Body Bias Tuning Scheme for Ultra Low-Power VLSI Systems.
IEEE Trans. on Circuits and Systems, 2018

Escalator Network for a 3D Chip Stack with Inductive Coupling ThruChip Interface.
IJNC, 2018

Analysis of Body Bias Control Using Overhead Conditions for Real Time Systems: A Practical Approach.
IEICE Transactions, 2018

Proxy Responses by FPGA-Based Switch for MapReduce Stragglers.
IEICE Transactions, 2018

Optimization of Body Biasing for Variable Pipelined Coarse-Grained Reconfigurable Architectures.
IEICE Transactions, 2018

A Coarse Grained-Reconfigurable Accelerator with energy efficient MTJ-based Non-volatile Flip-flops.
Proceedings of the 2018 International Conference on ReConFigurable Computing and FPGAs, 2018

Energy Efficient Write Verify and Retry Scheme for MTJ Based Flip-Flop and Application.
Proceedings of the IEEE 7th Non-Volatile Memory Systems and Applications Symposium, 2018

AxNoC: Low-power Approximate Network-on-Chips using Critical-Path Isolation.
Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip, 2018

Adaptive Body Bias Control Scheme for Ultra Low-Power Network-on-Chip Systems.
Proceedings of the 12th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2018

An Extension of A Temperature Modeling Tool HotSpot 6.0 for Castle-of-Chips Stacking.
Proceedings of the Sixth International Symposium on Computing and Networking, 2018

C4: An FPGA-based Compression Algorithm for ExpEther.
Proceedings of the Sixth International Symposium on Computing and Networking, 2018

An Trace-Driven Performance Prediction Method for Exploring NoC Design Optimization.
Proceedings of the Sixth International Symposium on Computing and Networking, 2018

k-Optimized Path Routing for High-Throughput Data Center Networks.
Proceedings of the Sixth International Symposium on Computing and Networking, 2018

Real Chip Evaluation of a Low Power CGRA with Optimized Application Mapping.
Proceedings of the 9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, 2018

Performance Estimation for Exascale Reconfigurable Dataflow Platforms.
Proceedings of the International Conference on Field-Programmable Technology, 2018

FPGA Design for Autonomous Vehicle Driving Using Binarized Neural Networks.
Proceedings of the International Conference on Field-Programmable Technology, 2018

Accelerator-in-Switch: A Novel Cooperation Framework for FPGAs and GPUs.
Proceedings of the International Conference on Field-Programmable Technology, 2018

A Configuration Data Multicasting Method for Coarse-Grained Reconfigurable Architectures.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

Performance Prediction for Large-Scale Heterogeneous Platforms.
Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

Superpixel Accelerator for Computer Vision Applications on Arria 10 SoC.
Proceedings of the 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2018

Design automation methodology of a critical path monitor for adaptive voltage controls.
Proceedings of the 2018 IEEE Symposium in Low-Power and High-Speed Chips, 2018

Deep Learning on High Performance FPGA Switching Boards: Flow-in-Cloud.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

Towards an Optimized Multi FPGA Architecture with STDM Network: A Preliminary Study.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

2017
Power Optimization Methodology for Ultralow Power Microcontroller With Silicon on Thin BOX MOSFET.
IEEE Trans. VLSI Syst., 2017

The First 25 Years of the FPL Conference: Significant Papers.
TRETS, 2017

Scalable Networks-on-Chip with Elastic Links Demarcated by Decentralized Routers.
IEEE Trans. Computers, 2017

Body Bias Domain Partitioning Size Exploration for a Coarse Grained Reconfigurable Accelerator.
IEICE Transactions, 2017

A Novel Channel Assignment Method to Ensure Deadlock-Freedom for Deterministic Routing.
IEICE Transactions, 2017

A Layout-Oriented Routing Method for Low-Latency HPC Networks.
IEICE Transactions, 2017

Level-Shifter-Less Approach for Multi-VDD SoC Design to Employ Body Bias Control in FD-SOI.
Proceedings of the VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things, 2017

Level-shifter-less approach for multi-VDD design to use body bias control in FD-SOI.
Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017

Glitch-aware variable pipeline optimization for CGRAs.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017

Implementation of Bitsliced AES Encryption on CUDA-Enabled GPU.
Proceedings of the Network and System Security - 11th International Conference, 2017

XYZ-Randomization using TSVs for Low-Latency Energy Efficient 3D-NoCs.
Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, 2017

The Design and Implementation of Scalable Deep Neural Network Accelerator Cores.
Proceedings of the 11th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2017

Multi-objective Optimization for Application Mapping and Body Bias Control on a CGRA.
Proceedings of the 11th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2017

3D Layout of Spidergon, Flattened Butterfly and Dragonfly on a Chip Stack with Inductive Coupling Through Chip Interface.
Proceedings of the 14th International Symposium on Pervasive Systems, 2017

Digital embedded memory scheme using voltage scaling and body bias separation for low-power system.
Proceedings of the International SoC Design Conference, 2017

Scalable deep neural network accelerator cores with cubic integration using through chip interface.
Proceedings of the International SoC Design Conference, 2017

An inductive-coupling link for 3-D Network-on-Chips.
Proceedings of the International SoC Design Conference, 2017

Building block operating system for 3D stacked computer systems with inductive coupling interconnect.
Proceedings of the International SoC Design Conference, 2017

Building block multi-chip systems using inductive coupling through chip interface.
Proceedings of the International SoC Design Conference, 2017

Order/Radix Problem: Towards Low End-to-End Latency Interconnection Networks.
Proceedings of the 46th International Conference on Parallel Processing, 2017

HiRy: An Advanced Theory on Design of Deadlock-Free Adaptive Routing for Arbitrary Topologies.
Proceedings of the 23rd IEEE International Conference on Parallel and Distributed Systems, 2017

Towards Tightly-coupled Datacenter with Free-space Optical Links.
Proceedings of the 2017 International Conference on Cloud and Big Data Computing, ICCBDC 2017, London, United Kingdom, September 17, 2017

A Practical Collision Avoidance Method for an Inter-Chip Bus with Wireless Inductive through Chip Interface.
Proceedings of the Fifth International Symposium on Computing and Networking, 2017

High-Bandwidth Low-Latency Approximate Interconnection Networks.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

Acceleration of the aggregation process in a Hall-thruster simulation using Intel FPGA SDK for OpenCL.
Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2017

Performance Evaluation of PEACH3: Field-Programmable Gate Array Switch for Tightly Coupled Accelerators.
Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2017

FPGA-based accelerator for losslessly quantized convolutional neural networks.
Proceedings of the International Conference on Field Programmable Technology, 2017

Accelerator-in-switch: A framework for tightly coupled switching hub and an accelerator with FPGA.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

In-switch approximate processing: Delayed tasks management for MapReduce applications.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Body bias optimization for variable pipelined CGRA.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Leveraging asymmetric body bias control for low power LSI design.
Proceedings of the 2017 IEEE Symposium in Low-Power and High-Speed Chips, 2017

Body bias control for renewable energy source with a high inner resistance.
Proceedings of the 2017 IEEE Symposium in Low-Power and High-Speed Chips, 2017

Panel discussions: "Cool chips for the next decade".
Proceedings of the 2017 IEEE Symposium in Low-Power and High-Speed Chips, 2017

A Case for Uni-directional Network Topologies in Large-Scale Clusters.
Proceedings of the 2017 IEEE International Conference on Cluster Computing, 2017

2016
Efficient 3-D Bus Architectures for Inductive-Coupling ThruChip Interfaces.
IEEE Trans. VLSI Syst., 2016

Novel Chip Stacking Methods to Extend Both Horizontally and Vertically for Many-Core Architectures with ThrouChip Interface.
IEICE Transactions, 2016

An Operating System Guided Fine-Grained Power Gating Control Based on Runtime Characteristics of Applications.
IEICE Transactions, 2016

Multi-Voltage Variable Pipeline Routers with the Same Clock Frequency for Low-Power Network-on-Chips Systems.
IEICE Transactions, 2016

Optical network technologies for HPC: computer-architects point of view.
IEICE Electronic Express, 2016

Randomizing Packet Memory Networks for Low-Latency Processor-Memory Communication.
Proceedings of the 24th Euromicro International Conference on Parallel, 2016

Acceleration of Full-PIC Simulation on a CPU-FPGA Tightly Coupled Environment.
Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016

On-the-Fly Data Compression/Decompression Mechanism with ExpEther.
Proceedings of the Fourth International Symposium on Computing and Networking, 2016

Vertical Packet Switching Elevator Network Using Inductive Coupling ThruChip Interface.
Proceedings of the Fourth International Symposium on Computing and Networking, 2016

Implementing Breadth-First Search on a Compact Supercomputer Suiren.
Proceedings of the Fourth International Symposium on Computing and Networking, 2016

LOREN: A Scalable Routing Method for Layout-Conscious Random Topologies.
Proceedings of the Fourth International Symposium on Computing and Networking, 2016

Trax solver on Zynq using incremental update algorithm.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

Variable pipeline structure for Coarse Grained Reconfigurable Array CMA.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

Body bias grain size exploration for a coarse grained reconfigurable accelerator.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Leveraging FDSOI through body bias domain partitioning and bias search.
Proceedings of the 53rd Annual Design Automation Conference, 2016

MuCCRA4-BB: A fine-grained body biasing capable DRP.
Proceedings of the 2016 IEEE Symposium in Low-Power and High-Speed Chips, 2016

From FLOPS to BYTES: disruptive change in high-performance computing towards the post-moore era.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

An inductive-coupling bus with collision detection scheme using magnetic field variation for 3-D network-on-chips.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

Zynq Cluster for CFD Parametric Survey.
Proceedings of the Applied Reconfigurable Computing - 12th International Symposium, 2016

ACRO: Assignment of channels in reverse order to make arbitrary routing deadlock-free.
Proceedings of the 15th IEEE/ACIS International Conference on Computer and Information Science, 2016

2015
Off-Loading LET Generation to PEACH2: A Switching Hub for High Performance GPU Clusters.
SIGARCH Computer Architecture News, 2015

Breadth First Search on Cost-efficient Multi-GPU Systems.
SIGARCH Computer Architecture News, 2015

A Toolchain for Dynamic Function Off-load on CPU-FPGA Platforms.
JIP, 2015

Courier: A Toolchain for Application Acceleration on Heterogeneous Platforms.
IPSJ Trans. System LSI Design Methodology, 2015

A Co-Processor Design for an Energy Efficient Reconfigurable Accelerator CMA.
IJNC, 2015

A Fine-Grained Power Gating Control on Linux Monitoring Power Consumption of Processor Functional Units.
IEICE Transactions, 2015

A Perpetuum Mobile 32bit CPU on 65nm SOTB CMOS Technology with Reverse-Body-Bias Assisted Sleep Mode.
IEICE Transactions, 2015

A 297mops/0.4mw ultra low power coarse-grained reconfigurable accelerator CMA-SOTB-2.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

Optimized Core-Links for Low-Latency NoCs.
Proceedings of the 23rd Euromicro International Conference on Parallel, 2015

On-Chip Decentralized Routers with Balanced Pipelines for Avoiding Interconnect Bottleneck.
Proceedings of the 9th International Symposium on Networks-on-Chip, 2015

3D Shared Bus Architecture Using Inductive Coupling Interconnect.
Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015

Expandable Chip Stacking Method for Many-core Architectures Consisting of Tiny Chips.
Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015

An optimal power supply and body bias voltage for a ultra low power micro-controller with silicon on thin box MOSFET.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Power Optimization Considering the Chip Temperature of Low Power Reconfigurable Accelerator CMA-SOTB.
Proceedings of the Third International Symposium on Computing and Networking, 2015

Trax solver on Zynq with Deep Q-Network.
Proceedings of the 2015 International Conference on Field Programmable Technology, 2015

7MOPS/lemon-battery image processing demonstration with an ultra-low power reconfigurable accelerator CMA-SOTB-2.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Significant papers from the first 25 years of the FPL conference.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Reduction calculator in an FPGA based switching Hub for high performance clusters.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Spatial and temporal granularity limits of body biasing in UTBB-FDSOI.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

A leakage current monitor circuit using silicon on thin BOX MOSFET for dynamic back gate bias control.
Proceedings of the 2015 IEEE Symposium in Low-Power and High-Speed Chips, 2015

Fined-grained body biasing for frequency scaling in advanced SOI processes.
Proceedings of the 2015 IEEE Symposium in Low-Power and High-Speed Chips, 2015

A metamorphotic Network-on-Chip for various types of parallel applications.
Proceedings of the 26th IEEE International Conference on Application-specific Systems, 2015

Towards Unification of Accelerated Computing and Interconnection For Extreme-Scale Computing.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

2014
3D NoC with Inductive-Coupling Links for Building-Block SiPs.
IEEE Trans. Computers, 2014

Performance Analysis of the Multi-GPU System with ExpEther.
SIGARCH Computer Architecture News, 2014

Accelerating Breadth First Search on GPU-BOX.
SIGARCH Computer Architecture News, 2014

Dynamic Power Consumption Optimization for Inductive-Coupling based Wireless 3D NoCs.
IPSJ Trans. System LSI Design Methodology, 2014

Reconfigurable Out-of-Order System for Fluid Dynamics Computation Using Unstructured Mesh.
IEICE Transactions, 2014

An Automatic Mixed Software Hardware Pipeline Builder for CPU-FPGA Platforms.
CoRR, 2014

Design of a low power NoC router using Marching Memory Through type.
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

A Thermal Management System for Building Block Computing Systems.
Proceedings of the IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs, 2014

Unbalanced buffer tree synthesis to suppress ground bounce for fine-grain power gating.
Proceedings of the 2014 International Symposium on System-on-Chip, 2014

FPGA Implementation of Viscous Function in a Package for Computational Fluid Dynamics.
Proceedings of the Second International Symposium on Computing and Networking, 2014

A Preliminarily Evaluation of PEACH3: A Switching Hub for Tightly Coupled Accelerators.
Proceedings of the Second International Symposium on Computing and Networking, 2014

A perpetuum mobile 32bit CPU on 65nm SOTB CMOS technology with reverse-body-bias assisted sleep mode.
Proceedings of the 2014 IEEE Hot Chips 26 Symposium (HCS), 2014

Hardware/software co-design architecture for Blokus Duo solver.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

Image processing by A 0.3V 2MW coarse-grained reconfigurable accelerator CMA-SOTB with a solar battery.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

Body bias control for a coarse grained reconfigurable accelerator implemented with Silicon on Thin BOX technology.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

A high speed design and implementation of dynamically reconfigurable processor using 28NM SOI technology.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Low-latency wireless 3D NoCs via randomized shortcut chips.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Design and evaluation of fine-grained power-gating for embedded microprocessors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

A low power NoC router using the marching memory through type.
Proceedings of the 2014 IEEE Symposium on Low-Power and High-Speed Chips, 2014

A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14µA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology.
Proceedings of the 2014 IEEE Symposium on Low-Power and High-Speed Chips, 2014

Design and control methodology for fine grain power gating based on energy characterization and code profiling of microprocessors.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface.
IEEE Micro, 2013

Design and Implementation of IP-based iSCSI Offload Engine on an FPGA.
IPSJ Trans. System LSI Design Methodology, 2013

Adaptive Flux Calculation Scheme in Advection Term Computation Using Partial Reconfiguration.
IJNC, 2013

Vertical Link On/Off Regulations for Inductive-Coupling Based Wireless 3-D NoCs.
IEICE Transactions, 2013

Fine-Grained Run-Tume Power Gating through Co-optimization of Circuit, Architecture, and System Software Design.
IEICE Transactions, 2013

High-Speed Fully-Adaptable CRC Accelerators.
IEICE Transactions, 2013

MCMA: A modular processing elements array based low-power coarse-grained reconfigurable accelerator.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

Headfirst sliding routing: A time-based routing scheme for bus-NoC hybrid 3-D architecture.
Proceedings of the 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2013

A Routing Strategy for Inductive-Coupling Based Wireless 3-D NoCs by Maximizing Topological Regularity.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2013

A Co-processor Design of an Energy Efficient Reconfigurable Accelerator CMA.
Proceedings of the First International Symposium on Computing and Networking, 2013

Tutorial: Introduction to Interconnection Networks from System Area Network to Network on Chips.
Proceedings of the First International Symposium on Computing and Networking, 2013

A speculative gather system for Cool Mega-Array.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Partially reconfigurable flux calculation scheme in advection term computation.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Artificial intelligence of Blokus Duo on FPGA using Cyber Work Bench.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

A low power reconfigurable accelerator using a back-gate bias control technique.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Task level pipelining with PEACH2: An FPGA switching fabric for high performance computing.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

A hardware complete detection mechanism for an energy efficient reconfigurable accelerator CMA.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

A fully pipelined FPGA architecture for stochastic simulation of chemical systems.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Demonstration of a heterogeneous multi-core processor with 3-D inductive coupling links.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface.
Proceedings of the 2013 IEEE Symposium on Low-Power and High-Speed Chips, 2013

Dynamic power on/off method for 3D NoCs with wireless inductive-coupling links.
Proceedings of the 2013 IEEE Symposium on Low-Power and High-Speed Chips, 2013

A case for wireless 3D NoCs for CMPs.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

An FPGA Acceleration for the Kd-tree Search in Photon Mapping.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2013

Research of PE Array Connection Network for Cool Mega-Array.
Proceedings of the 27th International Conference on Advanced Information Networking and Applications Workshops, 2013

An FPGA Implementation of Reconfigurable Real-Time Vision Architecture.
Proceedings of the 27th International Conference on Advanced Information Networking and Applications Workshops, 2013

A Circuit Division Method for High-Level Synthesis on Multi-FPGA Systems.
Proceedings of the 27th International Conference on Advanced Information Networking and Applications Workshops, 2013

2012
Geyser.
Proceedings of the Handbook of Energy-Aware and Green Computing - Two Volume Set., 2012

Partial Reconfiguration of Flux Limiter Functions in MUSCL Scheme Using FPGA.
IEICE Transactions, 2012

Foreword.
IEICE Transactions, 2012

An OpenCL Runtime Library for Embedded Multi-Core Accelerator.
Proceedings of the 2012 IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2012

Dynamically reconfigurable flux limiter functions in MUSCL scheme.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

Extension of Memory Controller Equipped with MuCCRA-3-DP: Dynamically Reconfigurable Processor Array.
Proceedings of the 15th International Conference on Network-Based Information Systems, 2012

Castle of Chips: A New Chip Stacking Structure with Wireless Inductive Coupling for Large Scale 3-D Multicore Systems.
Proceedings of the 15th International Conference on Network-Based Information Systems, 2012

Fine-Grained Power Control Using A Multi-Voltage Variable Pipeline Router.
Proceedings of the IEEE 6th International Symposium on Embedded Multicore/Manycore SoCs, 2012

Removing Context Memory from a Multi-context Dynamically Reconfigurable Processor.
Proceedings of the IEEE 6th International Symposium on Embedded Multicore/Manycore SoCs, 2012

A case for random shortcut topologies for HPC interconnects.
Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012

A Domain Specific Language and Toolchain for OpenCV Runtime Binary Acceleration Using GPU.
Proceedings of the Third International Conference on Networking and Computing, 2012

Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

A study of adaptable co-processors for Cyclic Redundancy Check on an FPGA.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

CMA-Cube: A scalable reconfigurable accelerator with 3-D wireless inductive coupling interconnect.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Reconfigurable out-of-order mechanism generator for unstructured grid computation in computational fluid dynamics.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Performance analysis of fully-adaptable CRC accelerators on an FPGA.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Trade-off analysis of fine-grained power gating methods for functional units in a CPU.
Proceedings of the 2012 IEEE Symposium on Low-Power and High-Speed Chips, 2012

A multi-Vdd dynamic variable-pipeline on-chip router for CMPs.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

Vertical Link On/Off Control Methods for Wireless 3-D NoCs.
Proceedings of the Architecture of Computing Systems - ARCS 2012 - 25th International Conference, Munich, Germany, February 28, 2012

Cost Effective Implementation of Flux Limiter Functions Using Partial Reconfiguration.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2012

2011
3-D NoC on Inductive Wireless Interconnect.
Proceedings of the 3D Integration for NoC-based SoC Architectures, 2011

A Switch-Tagged Routing Methodology for PC Clusters with VLAN Ethernet.
IEEE Trans. Parallel Distrib. Syst., 2011

Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

Prediction Router: A Low-Latency On-Chip Router Architecture with Multiple Predictors.
IEEE Trans. Computers, 2011

An implementation of out-of-order execution system for acceleration of computational fluid dynamics on FPGAs.
SIGARCH Computer Architecture News, 2011

High speed CRC with 64-bit generator polynomial on an FPGA.
SIGARCH Computer Architecture News, 2011

Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips.
IEEE Micro, 2011

An analytical network performance model for SIMD processor CSX600 interconnects.
Journal of Systems Architecture - Embedded Systems Design, 2011

Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units.
IPSJ Trans. System LSI Design Methodology, 2011

Design and Implementation of Echo Instructions for an Embedded Processor.
IPSJ Trans. System LSI Design Methodology, 2011

A Leakage Efficient Data TLB Design for Embedded Processors.
IEICE Transactions, 2011

Iterative Synthesis Methods Estimating Programmable-Wire Congestion in a Dynamically Reconfigurable Processor.
IEICE Transactions, 2011

A Leakage Efficient Instruction TLB Design for Embedded Processors.
IEICE Transactions, 2011

A Dynamic Link-Width Optimization for Network-on-Chip.
Proceedings of the 17th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2011

Power Centric Application Mapping for Dynamically Reconfigurable Processor Array with Dual Vdd and Dual Vth.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

A vertical bubble flow network using inductive-coupling for 3-D CMPs.
Proceedings of the NOCS 2011, 2011

On-chip detection methodology for break-even time of power gated function units.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

Vegeta: An Implementation and Evaluation of Development-Support Middleware on Multiple OpenCL Platform.
Proceedings of the Second International Conference on Networking and Computing, 2011

Proposal of Auto MPI Expansion Tool for Cell Broadband Engine Cluster.
Proceedings of the Second International Conference on Networking and Computing, 2011

Performance Evaluation of Power-Aware Multi-tree Ethernet for HPC Interconnects.
Proceedings of the Second International Conference on Networking and Computing, 2011

Cool Mega-Array: A highly energy efficient reconfigurable accelerator.
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

Reducing power for dynamically reconfigurable processor array by reducing number of reconfigurations.
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

The realtime image processing demonstration with CMA-1: An ultra low-power reconfigurable accelerator.
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

SLD-1(Silent Large Datapath): A ultra low power reconfigurable accelerator.
Proceedings of the 2011 IEEE Symposium on Low-Power and High-Speed Chips, 2011

Geyser-2: The second prototype CPU with fine-grained run-time power gating.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Dynamic VDD Switching Technique and Mapping Optimization in Dynamically Reconfigurable Processor for Efficient Energy Reduction.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011

Run-Time Power-Gating Techniques for Low-Power On-Chip Networks.
Proceedings of the Low Power Networks-on-Chip., 2011

2010
Implementation and evaluation of an arithmetic pipeline on FLOPS-2D: multi-FPGA system.
SIGARCH Computer Architecture News, 2010

Automatic Pipeline Construction Focused on Similarity of Rate Law Functions for an FPGA-based Biochemical Simulator.
IPSJ Trans. System LSI Design Methodology, 2010

Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs.
Proceedings of the NOCS 2010, 2010

A Deadlock-Free Non-minimal Fully Adaptive Routing Using Virtual Cut-Through Switching.
Proceedings of the Fifth International Conference on Networking, Architecture, and Storage, 2010

Stabilizing Path Modification of Power-Aware On/Off Interconnection Networks.
Proceedings of the Fifth International Conference on Networking, Architecture, and Storage, 2010

A variable-pipeline on-chip router optimized to traffic pattern.
Proceedings of the Third International Workshop on Network on Chip Architectures, 2010

Adaptive power gating for function units in a microprocessor.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Reducing instruction TLB's leakage power consumption for embedded processors.
Proceedings of the International Green Computing Conference 2010, 2010

Wire congestion aware synthesis for a dynamically reconfigurable processor.
Proceedings of the International Conference on Field-Programmable Technology, 2010

A datapath classification method for FPGA-based scientific application accelerator systems.
Proceedings of the International Conference on Field-Programmable Technology, 2010

Reducing power consumption for Dynamically Reconfigurable Processor Array with Partially Fixed Configuration Mapping.
Proceedings of the International Conference on Field-Programmable Technology, 2010

MuCCRA-3: a low power dynamically reconfigurable processor array.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Geyser-1: a MIPS R3000 CPU core with fine-grained run-time power gating.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

A Performance Evaluation of CUBE: One-Dimensional 512 FPGA Cluster.
Proceedings of the Reconfigurable Computing: Architectures, 2010

2009
Guest Editors' Introduction: ICFPT 2007.
TRETS, 2009

Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network.
IEEE Trans. Parallel Distrib. Syst., 2009

A Link Removal Methodology for Application-Specific Networks-on-Chip on FPGAs.
IEICE Transactions, 2009

Code Compression with Split Echo Instructions.
IEICE Transactions, 2009

Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

A Modular Approach to Heterogeneous Biochemical Model Simulation on an FPGA.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

An On/Off Link Activation Method for Power Regulation in InfiniBand.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2009

Performance Analysis of ClearSpeed's CSX600 Interconnects.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2009

Evaluation of a multicore reconfigurable architecture with variable core sizes.
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

An on/off link activation method for low-power ethernet in PC clusters.
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

Balanced Dimension-Order Routing for k-ary n-cubes.
Proceedings of the ICPPW 2009, 2009

Prediction router: Yet another low latency on-chip router architecture.
Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009

Leakage power reduction for coarse-grained dynamically reconfigurable processor arrays using Dual Vt cells.
Proceedings of the 2009 International Conference on Field-Programmable Technology, 2009

Fine Grain Partial Reconfiguration for energy saving in Dynamically Reconfigurable Processors.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Configuring area and performance: Empirical evaluation on an FPGA-based biochemical simulator.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Modularizing flux limiter functions for a Computational Fluid Dynamics accelerator on FPGAs.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Configuration with Self-Configured Datapath: A High Speed Configuration Method for Dynamically Reconfigurable Processors.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009

A Real Chip Evaluation of MuCCRA-3: A Low Power Dycamically Reconfigurable Processor Array.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009

Japanese Dynamically Reconfigurable Processors.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009

Cache Controller Design on Ultra Low Leakage Embedded Processors.
Proceedings of the Architecture of Computing Systems, 2009

Pipeline Scheduling with Input Port Constraints for an FPGA-Based Biochemical Simulator.
Proceedings of the Reconfigurable Computing: Architectures, 2009

2008
A Retargetable Compiler Based on Graph Representation for Dynamically Reconfigurable Processor Arrays.
IEICE Transactions, 2008

A Preemption Algorithm for a Multitasking Environment on Dynamically Reconfigurable Processors.
IEICE Transactions, 2008

A Mapping Method for Multi-Process Execution on Dynamically Reconfigurable Processors.
IEICE Transactions, 2008

Design and Implementation of Adaptive Viterbi Decoder for Using A Dynamic Reconfigurable Processor.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks.
Proceedings of the Second International Symposium on Networks-on-Chips, 2008

A Lightweight Fault-Tolerant Mechanism for Network-on-Chip.
Proceedings of the Second International Symposium on Networks-on-Chips, 2008

Three-Dimensional Layout of On-Chip Tree-Based Networks.
Proceedings of the 9th International Symposium on Parallel Architectures, 2008

A fine-grain dynamic sleep control scheme in MIPS R3000.
Proceedings of the 26th International Conference on Computer Design, 2008

Leakage power reduction for coarse grained dynamically reconfigurable processor arrays with fine grained Power Gating technique.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

Exploring the optimal size for multicasting configuration data of dynamically reconfigurable processors.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

Exploiting memory hierarchy for a Computational Fluid Dynamics accelerator on FPGAs.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

Practical implementation of a network-based stochastic biochemical simulation system on an FPGA.
Proceedings of the FPL 2008, 2008

A link removal methodology for Networks-on-Chip on reconfigurable systems.
Proceedings of the FPL 2008, 2008

Instruction buffer mode for multi-context Dynamically Reconfigurable Processors.
Proceedings of the FPL 2008, 2008

Power reduction techniques for Dynamically Reconfigurable Processor Arrays.
Proceedings of the FPL 2008, 2008

A Method for Capturing State Data on Dynamically Reconfigurable Processors.
Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2008

Evaluation of MuCCRA-D: A Dynamically Reconfigurable Processor with Directly Interconnected PEs.
Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2008

Run-time power gating of on-chip routers using look-ahead routing.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

A Preemption Algorithm for a Multitasking Environment on Dynamically Reconfigurable Processor.
Proceedings of the Reconfigurable Computing: Architectures, 2008

2007
Martini: A Network Interface Controller Chip for High Performance Computing with Distributed PCs.
IEEE Trans. Parallel Distrib. Syst., 2007

An Effective Design of Deadlock-Free Routing Algorithms Based on 2D Turn Model for Irregular Networks.
IEEE Trans. Parallel Distrib. Syst., 2007

A Port Combination Methodology for Application-Specific Networks-on-Chip on FPGAs.
IEICE Transactions, 2007

Data Multicasting Procedure for Increasing Configuration Speed of Coarse Grain Reconfigurable Devices.
IEICE Transactions, 2007

Implementation and Evaluation of Multicast Mechanism on Network Interface Plugged into a Memory Slot.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2007

Performance evaluation on low-latency communication mechanism of DIMMnet-2.
Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks, 2007

Performance, Cost, and Energy Evaluation of Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

Performance Improvement Methodology for ClearSpeed's CSX600.
Proceedings of the 2007 International Conference on Parallel Processing (ICPP 2007), 2007

Tightly-Coupled Multi-Layer Topologies for 3-D NoCs.
Proceedings of the 2007 International Conference on Parallel Processing (ICPP 2007), 2007

A Framework for Implementing a Network-Based Stochastic Biochemical Simulator on an FPGA.
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

A Mapping Method for Multi-Process Execution on Dynamically Reconfigurable Processors.
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

Overwrite Configuration Technique in Multicast Configuration Scheme for Dynamically Reconfigurable Processor Arrays.
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

FPGA Implementation of a Data-Driven Stochastic Biochemical Simulator with the Next Reaction Method.
Proceedings of the FPL 2007, 2007

A Combining technique of rate law functions for a cost-effective reconfigurable biological simulator.
Proceedings of the FPL 2007, 2007

A Temporal Correlation Based Port Combination Methodology for Networks-on-chip on Reconfigurable Systems.
Proceedings of the FPL 2007, 2007

A High Speed License Plate Recognition System on an FPGA.
Proceedings of the FPL 2007, 2007

Design Methodology and Trade-offs Analysis for Parameterized Dynamically Reconfigurable Processor Arrays.
Proceedings of the FPL 2007, 2007

Performance Analysis of Multi-process Execution Model on Dynamically Reconfigurable Processor.
Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2007

Implementation and Evaluation of a High Speed License Plate Recognition System on an FPGA.
Proceedings of the Seventh International Conference on Computer and Information Technology (CIT 2007), 2007

2006
A Simple Data Transfer Technique Using Local Address for Networks-on-Chips.
IEEE Trans. Parallel Distrib. Syst., 2006

A Survey on Dynamically Reconfigurable Processors.
IEICE Transactions, 2006

Enforcing Dimension-Order Routing in On-Chip Torus Networks Without Virtual Channels.
Proceedings of the Parallel and Distributed Processing and Applications, 2006

A cost-effective context memory structure for dynamically reconfigurable processors.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

Performance and power analysis of time-multiplexed execution on dynamically reconfigurable processor.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

Switch-tagged VLAN Routing Methodology for PC Clusters with Ethernet.
Proceedings of the 2006 International Conference on Parallel Processing (ICPP 2006), 2006

An adaptive Viterbi decoder on the dynamically reconfigurable processor.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

An FPGA Implementation of High Throughput Stochastic Simulator for Large-Scale Biochemical Systems.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Performance Evaluation of an Fpga-Based Biochemical Simulator ReCSip.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

A Context Dependent Clock Control Mechanism for Dynamically Reconfigurable Processors.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

A Parametric Study of Scalable Interconnects on FPGAs.
Proceedings of the 2006 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2006

Performance/Cost Trade-Off Evaluation for the DCT Implementation on the Dynamically Reconfigurable Processor.
Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006

A Virtual-Channel Free Mapping for Application-Specific On-Chip Torus Networks.
Proceedings of the ISCA 19th International Conference on Parallel and Distributed Computing Systems, 2006

2005
Performance Evaluation of Deterministic Routings, Multicasts, and Topologies on RHiNET-2 Cluster.
IEEE Trans. Parallel Distrib. Syst., 2005

The performance of SNAIL-2 (a SSS-MIN connected multiprocessor with cache coherent mechanism).
Parallel Computing, 2005

Path selection algorithm: the strategy for designing deterministic routing from alternative paths.
Parallel Computing, 2005

MMLRU Selection Function: A Simple and Efficient Output Selection Function in Adaptive Routing.
IEICE Transactions, 2005

Destination Bundle: A Routing Table Reduction Technique for Distributed Routing on Dependable Networks-on-Chips.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2005

Implementation of ISIS-SimpleScalar.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2005

A Packet Forwarding Layer for DIMMnet and its Hardware Implementation.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2005

Evaluation of Network Interface Controller on DIMMnet-2 Prototype Board.
Proceedings of the Sixth International Conference on Parallel and Distributed Computing, 2005

Implementation and Evaluation of the Mechanisms for Low Latency Communication on DIMMnet-2.
Proceedings of the High-Performance Computing - 6th International Symposium, 2005

Implementation of active direction-pass filter on dynamically reconfigurable processor.
Proceedings of the 2005 IEEE/RSJ International Conference on Intelligent Robots and Systems, 2005

An FPGA-Based, Multi-model Simulation Method for Biochemical Systems.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

Non-Minimal Routing Strategy for Application-Specific Networks-on-Chips.
Proceedings of the 34th International Conference on Parallel Processing Workshops (ICPP 2005 Workshops), 2005

VLAN-Based Minimal Paths in PC Cluster with Ethernet on Mesh and Torus.
Proceedings of the 34th International Conference on Parallel Processing (ICPP 2005), 2005

The Design of Scalable Stochastic Biochemical Simulator on FPGA.
Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

RoMultiC: Fast and Simple Configuration Data Multicasting Scheme for Coarse Grain Reconfigurable Devices.
Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

An Adaptive Cryptographic Accelerator for IPsec on Dynamically Reconfigurable Processor.
Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

A Framework for ODE-Based Multimodel Biochemical Simulations on an FPGA.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Efficient Scheduling of Rate Law Functions for ODE-Based Multimodel Biochemical Simulation on an FPGA.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

An I/O mechanism on a Dynamically Reconfigurable Processor - Which should be moved: Data or Configuration?
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Time-multiplexed execution on the dynamically reconfigurable processor: a performance/cost evaluation.
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

Performance and Cost Analysis of Time-Multiplexed Execution on the Dynamically Reconfigurable Processor.
Proceedings of the 13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 2005

Implementing core tasks of JPEG2000 Encoder on the Dynamically Reconfigurable Processor.
Proceedings of the 18th International Conference on Architecture of Computing Systems, 2005

2004
An FPGA-Based Acceleration Method for Metabolic Simulation.
IEICE Transactions, 2004

A New Memory Module for Memory Intensive Applications.
Proceedings of the 2004 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004), 2004

BLACK-BUS: A New Data-Transfer Technique Using Local Address on Networks-on-Chips.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

Stream applications on the dynamically reconfigurable processor.
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

Stochastic Simulation for Biochemical Reactions on FPGA.
Proceedings of the Field Programmable Logic and Application, 2004

Techniques for Virtual Hardware on a Dynamically Reconfigurable Processor - An Approach to Tough Cases.
Proceedings of the Field Programmable Logic and Application, 2004

Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor.
Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004

Folded Fat H-Tree: An Interconnection Topology for Dynamically Reconfigurable Processor Array.
Proceedings of the Embedded and Ubiquitous Computing, 2004

ReCSiP: a reconfigurable cell simulation platform: accelerating biological applications with FPGA.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

Future reconfigurable computing system.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

Design and Evaluation of a Switch Architecture for Multistage Interconnection Network with Temporary Directory.
Proceedings of the ISCA 17th International Conference on Parallel and Distributed Computing Systems, 2004

2003
Performance Evaluation of 3-Dimensional MIN with Cache Consistency Maintenance Mechanism.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2003

Performance Evaluation of Instruction Set Architecture of MBP-Light: A Distributed Memory Controller for a Large Scale Multiprocessor.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2003

Descending Layers Routing: A Deadlock-Free Deterministic Routing using Virtual Channels in System Area Networks with Irregular Topologies.
Proceedings of the 32nd International Conference on Parallel Processing (ICPP 2003), 2003

An implementation of the Rijndael on Async-WASMII.
Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003

Implementation of ReCSiP: A ReConfigurable Cell SImulation Platform.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

Reducing the Configuration Loading Time of a Coarse Grain Multicontext Reconfigurable Device.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

A Dynamically Adaptive Switching Fabric on a Multicontext Reconfigurable Device.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

Performance Evaluation of Routing Algorithms in RHiNET-2 Cluster.
Proceedings of the 2003 IEEE International Conference on Cluster Computing (CLUSTER 2003), 2003

Performance Evaluation of RHiNET-2/NI: A Network Interface for Distributed Parallel Computing Systems.
Proceedings of the 3rd IEEE International Symposium on Cluster Computing and the Grid (CCGrid 2003), 2003

MAPLE chip: a processing element for a static scheduling centric multiprocessor.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

Performance Evaluation of a Prototype of RHiNET-2: A Network-based Distributed Parallel Computing System.
Proceedings of the 21st IASTED International Multi-Conference on Applied Informatics (AI 2003), 2003

2002
Low Latency High Bandwidth Message Transfer Mechanisms for a Network Interface Plugged into a Memory Slot.
Cluster Computing, 2002

The Impact of Path Selection Algorithm of Adaptive Routing for Implementing Deterministic Routing.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2002

Low Latency Communication on DIMMnet-1 Network Interface Plugged into a DIMM Slot.
Proceedings of the 2002 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2002), 2002

Routing Algorithms Based on 2D Turn Model for Irregular Networks.
Proceedings of the International Symposium on Parallel Architectures, 2002

A General Hardware Design Model for Multicontext FPGAs.
Proceedings of the Field-Programmable Logic and Applications, 2002

RHiNET/NI: A Reconfigurable Network Interface for Cluster Computing.
Proceedings of the Field-Programmable Logic and Applications, 2002

2001
Recursive Diagonal Torus: An Interconnection Network for Massively Parallel Computers.
IEEE Trans. Parallel Distrib. Syst., 2001

A network switch for supporting high-performance parallel processing by computers distributed in local areas.
Systems and Computers in Japan, 2001

L-Turn Routing: An Adaptive Routing in Irregular Networks.
Proceedings of the 2001 International Conference on Parallel Processing, 2001

RHiNET-3/SW: an 80-Gbit/s high-speed network switch for distributed parallel computing.
Proceedings of the Ninth Symposium on High Performance Interconnects, 2001

The impact of output selection function on adaptive routing.
Proceedings of the ISCA 16th International Conference Computers and Their Applications, 2001

A prototype chip of multicontext FPGA with DRAM for virtual hardware.
Proceedings of ASP-DAC 2001, 2001

MMLRU Selection Function: An Output Selection Function on Adaptive Routing.
Proceedings of the ISCA 14th International Conference on Parallel and Distributed Computing Systems, 2001

2000
RHiNET-2/SW a Hight-throughput, Compact Network-switch Using 8.8-Gbit/s Optical Interconnection.
New Generation Comput., 2000

Coherence Protocol for Home Proxy Cache on RHiNET.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2000

On-the-fly Sending: A Low Latency High Bandwidth Message Transfer Mechanism.
Proceedings of the 5th International Symposium on Parallel Architectures, 2000

Environment for Multiprocessor Simulator Development.
Proceedings of the 5th International Symposium on Parallel Architectures, 2000

A Local Area System Network RHinet-1: A Network for High Performance Parallel Computing.
Proceedings of the Ninth IEEE International Symposium on High Performance Distributed Computing, 2000

Dataflow Partitioning and Scheduling Algorithms for WASMII, a Virtual Hardware.
Proceedings of the Field-Programmable Logic and Applications, 2000

Reconfigurable Systems: New Activities in Asia.
Proceedings of the Field-Programmable Logic and Applications, 2000

A Reconfigurable Stochastic Model Simulator for Analysis of Parallel Systems.
Proceedings of the 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 2000

A Virtual Hardware System on a Dynamically Reconfigurable Logic Device.
Proceedings of the 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 2000

MEMOnet : Network interface plugged into a memory slot.
Proceedings of the 2000 IEEE International Conference on Cluster Computing (CLUSTER 2000), November 28th, 2000

A floating point arithmetic unit for a static scheduling and compiler oriented multiprocessor system.
Proceedings of ASP-DAC 2000, 2000

1999
Performance evaluation of SNAIL: A multiprocessor based on the simple serial synchronized multistage interconnection network architecture.
Parallel Computing, 1999

An Educational System of LSI Design with Free-Wares for VDEC.
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 1999

A Torus Assignment for an Interconnection Network Recursive Diagonal Torus.
Proceedings of the 1999 International Symposium on Parallel Architectures, 1999

Implementation and Evaluation of the Compiler for WASMII, a Virtual Hardware System.
Proceedings of the 1999 International Conference on Parallel Processing Workshops, 1999

Internal Parallelization of Data-Driven Virtual Hardware.
Proceedings of the 1999 International Conference on Parallel Processing Workshops, 1999

ISIS: Multiprocessor Simulator Library.
Proceedings of the 17th IASTED International Conference on Applied Informatics, 1999

Floating Point Arithmetic Unit for the Custom Processor Maple.
Proceedings of the 17th IASTED International Conference on Applied Informatics, 1999

A Routing Algorithm for DS-WDM Ring.
Proceedings of the 17th IASTED International Conference on Applied Informatics, 1999

1998
An analysis of fairness and overhead in the arbitration protocol of the IEEE Futurebus standard.
Systems and Computers in Japan, 1998

Design and implementation of reconfigurable sensing system for networked robots.
Advanced Robotics, 1998

HOSMII: A Virtual Hardware Integrated with DRAM.
Proceedings of the Parallel and Distributed Processing, 10 IPPS/SPDP'98 Workshops Held in Conjunction with the 12th International Parallel Processing Symposium and 9th Symposium on Parallel and Distributed Processing, Orlando, Florida, USA, March 30, 1998

The MINC (Multistage Interconnection Network with Cache Control Mechanism) Chip.
Proceedings of the ASP-DAC '98, 1998

Reconfigurable Systems: Activities in Asia and South Pacific (Embedded Tutorial).
Proceedings of the ASP-DAC '98, 1998

1997
A study on snoop cache systems for single-chip multiprocessors.
Systems and Computers in Japan, 1997

Total System Image of the Reconfigurable Machine WASMII.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1997

Wavelength Division Multiple Access Ring - Virtual Topology on a Simple Ring Network.
Proceedings of the 1997 International Symposium on Parallel Architectures, 1997

Adaptive Routing on the Recursive Diagonal Torus.
Proceedings of the High Performance Computing, International Symposium, 1997

A reconfigurable sensor-data processing system for personal robots.
Proceedings of the Field-Programmable Logic and Applications, 7th International Workshop, 1997

Shared vs. Snoop: Evaluation of Cache Structure for Single-Chip Multiprocessors.
Proceedings of the Euro-Par '97 Parallel Processing, 1997

The RDT network router chip.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

An LSI implementation of the simple serial synchronized multistage interconnection network.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996
Recursive Diagonal Torus (RDT): An Interconnection Network for the Massively Parallel Computers.
Systems and Computers in Japan, 1996

Hot spot contention and message combining in the simple serial synchronized multistage interconnection network.
Proceedings of the Eighth IEEE Symposium on Parallel and Distributed Processing, 1996

An Emulation System of the WASMII: A Data Driven Computer on a Virtual Hardware.
Proceedings of the Field-Programmable Logic, 1996

ATTEMPT-1: A Reconfigurable Multiprocessor Testbed.
Proceedings of the Field-Programmable Logic, 1996

1995
WASMII: An MPLD with data-driven control on a virtual hardware.
The Journal of Supercomputing, 1995

An analysis of the hot spot contention and message combining on the simple serial synchronized-multistage interconnection network.
Systems and Computers in Japan, 1995

A Performance Evaluation of the Multiprocessor Testbed ATTEMPT-0.
Parallel Computing, 1995

Neural network parallel computing for multi-layer channel routing problems.
Neurocomputing, 1995

A Preprocessing System of the EULASH: An Environment for Efficient use of Multiprocessors with Local Memory.
Proceedings of the Seventh IASTED/ISMM International Conference on Parallel and Distributed Computing and Systems, 1995

Hierarchical Bit-Map Directory Schemes on the RDT Interconnection Network for a Massively Parallel Processor JUMP-1.
Proceedings of the 1995 International Conference on Parallel Processing, 1995

1994
Message transfer algorithms on the recursive diagonal torus.
Proceedings of the International Symposium on Parallel Architectures, 1994

Overview of the JUMP-1, an MPP prototype for general-purpose parallel computations.
Proceedings of the International Symposium on Parallel Architectures, 1994

SNAIL: A Multiprocessor Based on the Simple Serial Synchronized Multistage Interconnection Network Architecture.
Proceedings of the 1994 International Conference on Parallel Processing, 1994

Multistage Interconnection Networks with Multiple Outlets.
Proceedings of the 1994 International Conference on Parallel Processing, 1994

Software Environment for WASMII: a Data Driven Machine with a Virtual Hardware.
Proceedings of the Field-Programmable Logic, 1994

1993
A query-based parallel logic simulation algorithm.
Systems and Computers in Japan, 1993

Recursive Diagonal Torus: An Interconnection Network for Massively Parallel Computers.
Proceedings of the Fifth IEEE Symposium on Parallel and Distributed Processing, 1993

Performance evaluation of WASMII: a data driven computer on a virtual hardware.
Proceedings of the PARLE '93, 1993

1992
SSS (Simple Serial Synchronized)-MIN: A Novel Multi Stage Interconnection Architecture for Multiprocessors.
Proceedings of the Algorithms, Software, Architecture, 1992

A Parallel Logic Simulation Algorithm Based on Query.
Proceedings of the 1992 International Conference on Parallel Processing, 1992

1991
NCC: A concurrent description language for scientific calculation on multiprocessors.
Systems and Computers in Japan, 1991

A Batcher Double Omega Network with Combining.
Proceedings of the International Conference on Parallel Processing, 1991

1990
(SM)²-II: A Large-Scale Multiprocessor for Sparse Matrix Calculations.
IEEE Trans. Computers, 1990

A Fault Tolerant Batcher Network.
Proceedings of the 1990 International Conference on Parallel Processing, 1990

1989
A static scheduling system for a parallel machine (SM)2-II.
Proceedings of the PARLE '89: Parallel Architectures and Languages Europe, 1989

A New Version of a Parallel Production System Machine, MANJI-II.
Proceedings of the Database Machines, Sixth International Workshop, 1989

Cache with Synchronization Mechanism.
Proceedings of the Information Processing 89, Proceedings of the IFIP 11th World Computer Congress, San Francisco, USA, August 28, 1989

1988
IMPULSE: A High Performance Processing Unit for Multiprocessors for Scientific Calculation.
Proceedings of the 15th Annual International Symposium on Computer Architecture, 1988

1987
A Shared Memory Architecture for MANJI Production System Machine.
Proceedings of the Database Machines and Knowledge Base Machines, 1987

1986
Dynamic fault recovery in mesh-connected parallel computers.
Systems and Computers in Japan, 1986

An Adaptable Cluster Structure of (SM)²-II.
Proceedings of the CONPAR 86: Conference on Algorithms and Hardware for Parallel Processing, 1986

1985
Performance analysis of parallel machines using multi-read memory.
Systems and Computers in Japan, 1985

(SM)²-II: A New Version of the Sparse Matrix Solving Machine.
Proceedings of the 12th Annual Symposium on Computer Architecture, 1985

1983
(SM)2: Sparse Matrix Solving Machine
Proceedings of the 10th Annual Symposium on Computer Architecture, 1983, 1983


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