Michihiro Koibuchi

According to our database1, Michihiro Koibuchi authored at least 172 papers between 2001 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of two.

Timeline

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Bibliography

2022
A Scalable Distributed Radix Sorter for FPGA Clusters using High-Bandwidth Memory Networks.
Proceedings of the 30th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2022

2021
OPTWEB: A Lightweight Fully Connected Inter-FPGA Network for Efficient Collectives.
IEEE Trans. Computers, 2021

An FPGA-Based Optimizer Design for Distributed Deep Learning with Multiple GPUs.
IEICE Trans. Inf. Syst., 2021

Improving the Performance of Circuit-Switched Interconnection Network for a Multi-FPGA System.
IEICE Trans. Inf. Syst., 2021

Low-Latency Low-Energy Memory-Cube Networks using Dual-Voltage Datapaths.
Proceedings of the 29th Euromicro International Conference on Parallel, 2021

A Case for Low-Latency Network-on-Chip using Compression Routers.
Proceedings of the 29th Euromicro International Conference on Parallel, 2021

Accelerating Parallel Sort on Tightly-Coupled FPGAs enabled by Onboard Si-Photonics Transceivers.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2021

Accelerating MPI Communication Using Floating-point Compression on Lossy Interconnection Networks.
Proceedings of the 46th IEEE Conference on Local Computer Networks, 2021

The Case for Disjoint Job Mapping on High-Radix Networked Parallel Computers.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2021

Low-Latency High-Bandwidth Interconnection Networks by Selective Packet Compression.
Proceedings of the Ninth International Symposium on Computing and Networking, 2021

Packet Forwarding Cache of Commodity Switches for Parallel Computers.
Proceedings of the IEEE International Conference on Cluster Computing, 2021

GPU Parallelization of All-Pairs-Shortest-Path Algorithm in Low-Degree Unweighted Regular Graph.
Proceedings of the ACIT 2021: The 8th International Virtual Conference on Applied Computing & Information Technology, Kanazawa, Japan, June 20, 2021

2020
Traffic-Independent Multi-Path Routing for High-Throughput Data Center Networks.
IEICE Trans. Inf. Syst., 2020

Application Mapping and Scheduling of Uncertain Communication Patterns onto Non-Random and Random Network Topologies.
IEICE Trans. Inf. Syst., 2020

Efficient Two-Opt Collective-Communication Operations on Low-Latency Random Network Topologies.
IEICE Trans. Inf. Syst., 2020

A Generalized Theory Based on the Turn Model for Deadlock-Free Irregular Networks.
IEICE Trans. Inf. Syst., 2020

Accelerating Deep Learning using Multiple GPUs and FPGA-Based 10GbE Switch.
Proceedings of the 28th Euromicro International Conference on Parallel, 2020

Implementing a Multi-ejection Switch and Making the Use of Multiple Lanes in a Circuit-switched Multi-FPGA System.
Proceedings of the Eighth International Symposium on Computing and Networking Workshops, 2020

A Diagonal Checksum Algorithm-Based Fault Tolerance for Parallel Matrix Multiplication.
Proceedings of the Eighth International Symposium on Computing and Networking Workshops, 2020

Dual-Plane Isomorphic Hypercube Network.
Proceedings of the International Conference on High Performance Computing in Asia-Pacific Region, 2020

2019
Designing High-Performance Interconnection Networks with Host-Switch Graphs.
IEEE Trans. Parallel Distributed Syst., 2019

Foreword.
IEICE Trans. Inf. Syst., 2019

Optimizing Slot Utilization and Network Topology for Communication Pattern on Circuit-Switched Parallel Computing Systems.
IEICE Trans. Inf. Syst., 2019

Low-Latency Error-Prone Optical Networks for Fast Approximate Computation on High-End Datacenters.
Proceedings of the 2019 24th OptoElectronics and Communications Conference (OECC) and 2019 International Conference on Photonics in Switching and Computing (PSC), 2019

A STDM (Static Time Division Multiplexing) Switch on a Multi-FPGA System.
Proceedings of the 13th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2019

The Impact of Application Mapping on Non-Random and Random Network Topologies.
Proceedings of the 2019 IEEE Intl Conf on Parallel & Distributed Processing with Applications, 2019

The Case for Water-Immersion Computer Boards.
Proceedings of the 48th International Conference on Parallel Processing, 2019

Diameter/ASPL-Based Mapping of Applications with Uncertain Communication over Random Interconnection Networks.
Proceedings of the 25th IEEE International Conference on Parallel and Distributed Systems, 2019

Sparse 3-D NoCs with Inductive Coupling.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
Proxy Responses by FPGA-Based Switch for MapReduce Stragglers.
IEICE Trans. Inf. Syst., 2018

Enhancing Job Scheduling on Inter-Rackscale Datacenters with Free-Space Optical Links.
IEICE Trans. Inf. Syst., 2018

AxNoC: Low-power Approximate Network-on-Chips using Critical-Path Isolation.
Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip, 2018

Low-Reliable Low-Latency Networks Optimized for HPC Parallel Applications.
Proceedings of the 17th IEEE International Symposium on Network Computing and Applications, 2018

Adaptive Body Bias Control Scheme for Ultra Low-Power Network-on-Chip Systems.
Proceedings of the 12th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2018

An Extension of A Temperature Modeling Tool HotSpot 6.0 for Castle-of-Chips Stacking.
Proceedings of the Sixth International Symposium on Computing and Networking, 2018

An Trace-Driven Performance Prediction Method for Exploring NoC Design Optimization.
Proceedings of the Sixth International Symposium on Computing and Networking, 2018

The Impact of Job Mapping on Random Network Topology.
Proceedings of the Sixth International Symposium on Computing and Networking, 2018

Performance Evaluation of Collective Communication on Random Network Topology.
Proceedings of the Sixth International Symposium on Computing and Networking, 2018

2017
Distributed Shortcut Networks: Low-Latency Low-Degree Non-Random Topologies Targeting the Diameter and Cable Length Trade-Off.
IEEE Trans. Parallel Distributed Syst., 2017

Scalable Networks-on-Chip with Elastic Links Demarcated by Decentralized Routers.
IEEE Trans. Computers, 2017

A Novel Channel Assignment Method to Ensure Deadlock-Freedom for Deterministic Routing.
IEICE Trans. Inf. Syst., 2017

A Layout-Oriented Routing Method for Low-Latency HPC Networks.
IEICE Trans. Inf. Syst., 2017

A Case of Electrical Circuit Switched Interconnection Network for Parallel Computers.
Proceedings of the 18th International Conference on Parallel and Distributed Computing, 2017

3D Layout of Spidergon, Flattened Butterfly and Dragonfly on a Chip Stack with Inductive Coupling Through Chip Interface.
Proceedings of the 14th International Symposium on Pervasive Systems, 2017

Order/Radix Problem: Towards Low End-to-End Latency Interconnection Networks.
Proceedings of the 46th International Conference on Parallel Processing, 2017

HiRy: An Advanced Theory on Design of Deadlock-Free Adaptive Routing for Arbitrary Topologies.
Proceedings of the 23rd IEEE International Conference on Parallel and Distributed Systems, 2017

Towards Tightly-coupled Datacenter with Free-space Optical Links.
Proceedings of the 2017 International Conference on Cloud and Big Data Computing, ICCBDC 2017, London, United Kingdom, September 17, 2017

SINET5: A low-latency and high-bandwidth backbone network for SDN/NFV Era.
Proceedings of the IEEE International Conference on Communications, 2017

High-Bandwidth Low-Latency Approximate Interconnection Networks.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

In-switch approximate processing: Delayed tasks management for MapReduce applications.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

A Case for Uni-directional Network Topologies in Large-Scale Clusters.
Proceedings of the 2017 IEEE International Conference on Cluster Computing, 2017

Cable-geometric error-prone approach for low-latency interconnection networks.
Proceedings of the 17th IEEE/ACM International Symposium on Cluster, 2017

2016
Efficient 3-D Bus Architectures for Inductive-Coupling ThruChip Interfaces.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Layout-Conscious Expandable Topology for Low-Degree Interconnection Networks.
IEICE Trans. Inf. Syst., 2016

Novel Chip Stacking Methods to Extend Both Horizontally and Vertically for Many-Core Architectures with ThrouChip Interface.
IEICE Trans. Inf. Syst., 2016

Job Mapping and Scheduling on Free-Space Optical Networks.
IEICE Trans. Inf. Syst., 2016

Multi-Voltage Variable Pipeline Routers with the Same Clock Frequency for Low-Power Network-on-Chips Systems.
IEICE Trans. Electron., 2016

Optical network technologies for HPC: computer-architects point of view.
IEICE Electron. Express, 2016

A diagonal cabling approach to data center and HPC systems.
Proceedings of the Seventh Symposium on Information and Communication Technology, 2016

Randomizing Packet Memory Networks for Low-Latency Processor-Memory Communication.
Proceedings of the 24th Euromicro International Conference on Parallel, 2016

Suitability of the Random Topology for HPC Applications.
Proceedings of the 24th Euromicro International Conference on Parallel, 2016

A fully meshed backbone network for data-intensive sciences and SDN services.
Proceedings of the Eighth International Conference on Ubiquitous and Future Networks, 2016

Randomly Optimized Grid Graph for Low-Latency Interconnection Networks.
Proceedings of the 45th International Conference on Parallel Processing, 2016

Deterministic Construction of Regular Geometric Graphs with Short Average Distance and Limited Edge Length.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2016

Towards Ideal Hop Counts in Interconnection Networks with Arbitrary Size.
Proceedings of the Fourth International Symposium on Computing and Networking, 2016

An Interconnection Network Exploiting Trade-Off between Routing Table Size and Path Length.
Proceedings of the Fourth International Symposium on Computing and Networking, 2016

LOREN: A Scalable Routing Method for Layout-Conscious Random Topologies.
Proceedings of the Fourth International Symposium on Computing and Networking, 2016

HPC Job Mapping over Reconfigurable Wireless Links.
Proceedings of the IEEE/ACM 16th International Symposium on Cluster, 2016

ACRO: Assignment of channels in reverse order to make arbitrary routing deadlock-free.
Proceedings of the 15th IEEE/ACIS International Conference on Computer and Information Science, 2016

2015
Swap-And-Randomize: A Method for Building Low-Latency HPC Interconnects.
IEEE Trans. Parallel Distributed Syst., 2015

New Directions for a Japanese Academic Backbone Network.
IEICE Trans. Inf. Syst., 2015

The Case for Network Coding for Collective Communication on HPC Interconnection Networks.
IEICE Trans. Inf. Syst., 2015

Singularity of Future Computer-System Networks.
Proceedings of the Sixth International Symposium on Information and Communication Technology, 2015

Optimized Core-Links for Low-Latency NoCs.
Proceedings of the 23rd Euromicro International Conference on Parallel, 2015

On-Chip Decentralized Routers with Balanced Pipelines for Avoiding Interconnect Bottleneck.
Proceedings of the 9th International Symposium on Networks-on-Chip, 2015

Expandable Chip Stacking Method for Many-core Architectures Consisting of Tiny Chips.
Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015

Enabling Ideal Job Mapping on Wireless Supercomputers and Datacenters.
Proceedings of the Third International Symposium on Computing and Networking, 2015

Augmenting low-latency HPC network with free-space optical links.
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

A metamorphotic Network-on-Chip for various types of parallel applications.
Proceedings of the 26th IEEE International Conference on Application-specific Systems, 2015

2014
Highly available network design and resource management of SINET4.
Telecommun. Syst., 2014

3D NoC with Inductive-Coupling Links for Building-Block SiPs.
IEEE Trans. Computers, 2014

Extreme Big Data (EBD): Next Generation Big Data Infrastructure Technologies Towards Yottabyte/Year.
Supercomput. Front. Innov., 2014

Dynamic Power Consumption Optimization for Inductive-Coupling based Wireless 3D NoCs.
IPSJ Trans. Syst. LSI Des. Methodol., 2014

Hierarchical Network Coding for Collective Communication on HPC Interconnects.
Proceedings of the 22nd Euromicro International Conference on Parallel, 2014

Skywalk: A Topology for HPC Networks with Low-Delay Switches.
Proceedings of the 2014 IEEE 28th International Parallel and Distributed Processing Symposium, 2014

Layout-aware expandable low-degree topology.
Proceedings of the 20th IEEE International Conference on Parallel and Distributed Systems, 2014

Darkfiber Planning for Extensible HPC Network Design under Uncertainties.
Proceedings of the Second International Symposium on Computing and Networking, 2014

Low-latency wireless 3D NoCs via randomized shortcut chips.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Many-cores and On-chip Interconnects (NII Shonan Meeting 2013-8).
NII Shonan Meet. Rep., 2013

A Fully Optical Ring Network-on-Chip with Static and Dynamic Wavelength Allocation.
IEICE Trans. Inf. Syst., 2013

Headfirst sliding routing: A time-based routing scheme for bus-NoC hybrid 3-D architecture.
Proceedings of the 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2013

PopCache: Cache more or less based on content popularity for information-centric networking.
Proceedings of the 38th Annual IEEE Conference on Local Computer Networks, 2013

Distributed Shortcut Networks: Layout-Aware Low-Degree Topologies Exploiting Small-World Effect.
Proceedings of the 42nd International Conference on Parallel Processing, 2013

A Routing Strategy for Inductive-Coupling Based Wireless 3-D NoCs by Maximizing Topological Regularity.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2013

Future Low-Latency Networks for High Performance Computing.
Proceedings of the First International Symposium on Computing and Networking, 2013

Layout-conscious random topologies for HPC off-chip interconnects.
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

Dynamic power on/off method for 3D NoCs with wireless inductive-coupling links.
Proceedings of the 2013 IEEE Symposium on Low-Power and High-Speed Chips, 2013

A case for wireless 3D NoCs for CMPs.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
A Survey and Evaluation of Topology-Agnostic Deterministic Routing Algorithms.
IEEE Trans. Parallel Distributed Syst., 2012

Cabinet Layout Optimization of Supercomputer Topologies for Shorter Cable Length.
Proceedings of the 13th International Conference on Parallel and Distributed Computing, 2012

Fine-Grained Power Control Using A Multi-Voltage Variable Pipeline Router.
Proceedings of the IEEE 6th International Symposium on Embedded Multicore/Manycore SoCs, 2012

Throttling Control for Bufferless Routing in On-chip Networks.
Proceedings of the IEEE 6th International Symposium on Embedded Multicore/Manycore SoCs, 2012

A case for random shortcut topologies for HPC interconnects.
Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012

A multi-Vdd dynamic variable-pipeline on-chip router for CMPs.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

On incentive-based inter-domain caching for content delivery in future internet architectures.
Proceedings of the Asian Internet Engineering Conference, 2012

2011
3-D NoC on Inductive Wireless Interconnect.
Proceedings of the 3D Integration for NoC-based SoC Architectures, 2011

A Switch-Tagged Routing Methodology for PC Clusters with VLAN Ethernet.
IEEE Trans. Parallel Distributed Syst., 2011

Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Prediction Router: A Low-Latency On-Chip Router Architecture with Multiple Predictors.
IEEE Trans. Computers, 2011

An analytical network performance model for SIMD processor CSX600 interconnects.
J. Syst. Archit., 2011

An Efficient Path Setup for a Hybrid Photonic Network-on-Chip.
Int. J. Netw. Comput., 2011

A Dynamic Link-Width Optimization for Network-on-Chip.
Proceedings of the 17th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2011

A vertical bubble flow network using inductive-coupling for 3-D CMPs.
Proceedings of the NOCS 2011, 2011

Performance Evaluation of Power-Aware Multi-tree Ethernet for HPC Interconnects.
Proceedings of the Second International Conference on Networking and Computing, 2011

Impact of Tohoku earthquake on R&E network in Japan.
Proceedings of the Special Workshop on Internet and Disasters, 2011

Run-Time Power-Gating Techniques for Low-Power On-Chip Networks.
Proceedings of the Low Power Networks-on-Chip., 2011

2010
Dynamic Resource Allocation and QoS Control Capabilities of the Japanese Academic Backbone Network.
Future Internet, 2010

Hardware Architecture for Supporting High-speed Database Insertion on Service-oriented Router for Future Internet.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2010

Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs.
Proceedings of the NOCS 2010, 2010

A Deadlock-Free Non-minimal Fully Adaptive Routing Using Virtual Cut-Through Switching.
Proceedings of the Fifth International Conference on Networking, Architecture, and Storage, 2010

Stabilizing Path Modification of Power-Aware On/Off Interconnection Networks.
Proceedings of the Fifth International Conference on Networking, Architecture, and Storage, 2010

A variable-pipeline on-chip router optimized to traffic pattern.
Proceedings of the Third International Workshop on Network on Chip Architectures, 2010

A Regular Expression Processor Embedded in Service-Friendly Router for Future Internet.
Proceedings of the 39th International Conference on Parallel Processing, 2010

An Efficient Path Setup for a Photonic Network-on-Chip.
Proceedings of the First International Conference on Networking and Computing, 2010

2009
Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network.
IEEE Trans. Parallel Distributed Syst., 2009

Impact of QoS operations on an experimental testbed network.
Simul. Model. Pract. Theory, 2009

Design of versatile academic infrastructure for multilayer network services.
IEEE J. Sel. Areas Commun., 2009

A Link Removal Methodology for Application-Specific Networks-on-Chip on FPGAs.
IEICE Trans. Inf. Syst., 2009

An On/Off Link Activation Method for Power Regulation in InfiniBand.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2009

Performance Analysis of ClearSpeed's CSX600 Interconnects.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2009

Efficient Scheduling Algorithms on Bandwidth Reservation Service of Internet Using Metaheuristics.
Proceedings of the Ninth International Conference on Intelligent Systems Design and Applications, 2009

An on/off link activation method for low-power ethernet in PC clusters.
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

Balanced Dimension-Order Routing for k-ary n-cubes.
Proceedings of the ICPPW 2009, 2009

Implementation and Evaluation of Layer-1 Bandwidth-on-Demand Capabilities in SINET3.
Proceedings of IEEE International Conference on Communications, 2009

Prediction router: Yet another low latency on-chip router architecture.
Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009

2008
Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks.
Proceedings of the Second International Symposium on Networks-on-Chips, 2008

A Lightweight Fault-Tolerant Mechanism for Network-on-Chip.
Proceedings of the Second International Symposium on Networks-on-Chips, 2008

Three-Dimensional Layout of On-Chip Tree-Based Networks.
Proceedings of the 9th International Symposium on Parallel Architectures, 2008

A link removal methodology for Networks-on-Chip on reconfigurable systems.
Proceedings of the FPL 2008, 2008

Impact of topology and link aggregation on a PC cluster with Ethernet.
Proceedings of the 2008 IEEE International Conference on Cluster Computing, 29 September, 2008

Run-time power gating of on-chip routers using look-ahead routing.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
An Effective Design of Deadlock-Free Routing Algorithms Based on 2D Turn Model for Irregular Networks.
IEEE Trans. Parallel Distributed Syst., 2007

A Port Combination Methodology for Application-Specific Networks-on-Chip on FPGAs.
IEICE Trans. Inf. Syst., 2007

Architectural Design of Next-Generation Science Information Network.
IEICE Trans. Commun., 2007

Performance, Cost, and Energy Evaluation of Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

Performance Improvement Methodology for ClearSpeed's CSX600.
Proceedings of the 2007 International Conference on Parallel Processing (ICPP 2007), 2007

Tightly-Coupled Multi-Layer Topologies for 3-D NoCs.
Proceedings of the 2007 International Conference on Parallel Processing (ICPP 2007), 2007

Investigating QoS Performance on a Testbed Network.
Proceedings of the 16th International Conference on Computer Communications and Networks, 2007

Layer-1 Bandwidth on Demand Services in SINET3.
Proceedings of the Global Communications Conference, 2007

A Temporal Correlation Based Port Combination Methodology for Networks-on-chip on Reconfigurable Systems.
Proceedings of the FPL 2007, 2007

2006
A Simple Data Transfer Technique Using Local Address for Networks-on-Chips.
IEEE Trans. Parallel Distributed Syst., 2006

Enforcing Dimension-Order Routing in On-Chip Torus Networks Without Virtual Channels.
Proceedings of the Parallel and Distributed Processing and Applications, 2006

Switch-tagged VLAN Routing Methodology for PC Clusters with Ethernet.
Proceedings of the 2006 International Conference on Parallel Processing (ICPP 2006), 2006

A Parametric Study of Scalable Interconnects on FPGAs.
Proceedings of the 2006 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2006

A Virtual-Channel Free Mapping for Application-Specific On-Chip Torus Networks.
Proceedings of the ISCA 19th International Conference on Parallel and Distributed Computing Systems, 2006

2005
Performance Evaluation of Deterministic Routings, Multicasts, and Topologies on RHiNET-2 Cluster.
IEEE Trans. Parallel Distributed Syst., 2005

Path selection algorithm: the strategy for designing deterministic routing from alternative paths.
Parallel Comput., 2005

Enforcing in-order packet delivery in system area networks with adaptive routing.
J. Parallel Distributed Comput., 2005

MMLRU Selection Function: A Simple and Efficient Output Selection Function in Adaptive Routing.
IEICE Trans. Inf. Syst., 2005

Destination Bundle: A Routing Table Reduction Technique for Distributed Routing on Dependable Networks-on-Chips.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2005

In-Order Packet Delivery in Interconnection Networks using Adaptive Routing.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

Non-Minimal Routing Strategy for Application-Specific Networks-on-Chips.
Proceedings of the 34th International Conference on Parallel Processing Workshops (ICPP 2005 Workshops), 2005

VLAN-Based Minimal Paths in PC Cluster with Ethernet on Mesh and Torus.
Proceedings of the 34th International Conference on Parallel Processing (ICPP 2005), 2005

2004
BLACK-BUS: A New Data-Transfer Technique Using Local Address on Networks-on-Chips.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

Folded Fat H-Tree: An Interconnection Topology for Dynamically Reconfigurable Processor Array.
Proceedings of the Embedded and Ubiquitous Computing, 2004

2003
Descending Layers Routing: A Deadlock-Free Deterministic Routing using Virtual Channels in System Area Networks with Irregular Topologies.
Proceedings of the 32nd International Conference on Parallel Processing (ICPP 2003), 2003

Performance Evaluation of Routing Algorithms in RHiNET-2 Cluster.
Proceedings of the 2003 IEEE International Conference on Cluster Computing (CLUSTER 2003), 2003

2002
The Impact of Path Selection Algorithm of Adaptive Routing for Implementing Deterministic Routing.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2002

Routing Algorithms Based on 2D Turn Model for Irregular Networks.
Proceedings of the International Symposium on Parallel Architectures, 2002

2001
L-Turn Routing: An Adaptive Routing in Irregular Networks.
Proceedings of the 2001 International Conference on Parallel Processing, 2001

The impact of output selection function on adaptive routing.
Proceedings of the ISCA 16th International Conference Computers and Their Applications, 2001

MMLRU Selection Function: An Output Selection Function on Adaptive Routing.
Proceedings of the ISCA 14th International Conference on Parallel and Distributed Computing Systems, 2001


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