Daisuke Kanemoto

According to our database, Daisuke Kanemoto authored at least 30 papers between 2008 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Noise-Masking Cryptosystem Using Watermark and Chain Generation for EEG Measurement with Compressed Sensing.

Ryota Tsunaga, Daisuke Kanemoto, Tetsuya Hirose

Proceedings of the IEEE International Conference on Consumer Electronics, 2024

Utilizing Previously Acquired BSBL Algorithm Parameters in the Compressed Sensing Framework for EEG Measurements.

Takuya Miyata, Daisuke Kanemoto, Tetsuya Hirose

Proceedings of the IEEE International Conference on Consumer Electronics, 2024

2023

Random Undersampling Wireless EEG Measurement Device using a Small TEG.

Takuya Miyata, Daisuke Kanemoto, Tetsuya Hirose

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

EEG Measurements with Compressed Sensing Utilizing EEG Signals as the Basis Matrix.

Daisuke Kanemoto, Tetsuya Hirose

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

A Programmable Differential Bandgap Reference for Ultra-Low-Power IoT Edge Node Devices.

Yoshinori Itotagawa, Koma Atsumi, Hikaru Sebe, Daisuke Kanemoto, Tetsuya Hirose

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Sub-30-mV-Supply, Fully Integrated Ring Oscillator Consisting of Recursive Stacking Body-Bias Inverters for Extremely Low-Voltage Energy Harvesting.

Hikaru Sebe, Tomohisa Okumura, Shintaro Sumi, Daisuke Kanemoto, Po-Hung Chen, Tetsuya Hirose

Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

2022

Compressed Sensing EEG Measurement Technique with Normally Distributed Sampling Series.

Yuki Okabe, Daisuke Kanemoto, Osamu Maida, Tetsuya Hirose

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., October, 2022

Image Quality Improvement for Capsule Endoscopy Based on Compressed Sensing with K-SVD Dictionary Learning.

Yuuki Harada, Daisuke Kanemoto, Takahiro Inoue, Osamu Maida, Tetsuya Hirose

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022

Sub-50-mV Charge Pump and its Driver for Extremely Low-Voltage Thermal Energy Harvesting.

Hikaru Sebe, Daisuke Kanemoto, Tetsuya Hirose

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021

Applying K-SVD Dictionary Learning for EEG Compressed Sensing Framework with Outlier Detection and Independent Component Analysis.

Kotaro Nagai, Daisuke Kanemoto, Makoto Ohki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021

A 35-mV supply ring oscillator consisting of stacked body bias inverters for extremely low-voltage LSIs.

Masaya Nishi, Kaori Matsumoto, Nobutaka Kuroki, Masahiro Numa, Hikaru Sebe, Ryo Matsuzuka, Osamu Maida, Daisuke Kanemoto, Tetsuya Hirose

IEICE Electron. Express, 2021

2020

Compressed Sensing Framework Applying Independent Component Analysis after Undersampling for Reconstructing Electroencephalogram Signals.

Daisuke Kanemoto, Shun Katsumata, Masao Aihara, Makoto Ohki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2020

An 11.8 nA ultra-low power active diode using a hysteresis common gate comparator for low-power energy harvesting systems.

Kaori Matsumoto, Hiroki Asano, Yuichiro Nakazawa, Nobutaka Kuroki, Masahiro Numa, Osamu Maida, Daisuke Kanemoto, Tetsuya Hirose

IEICE Electron. Express, 2020

A 34-mV Startup Ring Oscillator Using Stacked Body Bias Inverters for Extremely Low-Voltage Thermoelectric Energy Harvesting.

Masaya Nishi, Kaori Matsumoto, Nobutaka Kuroki, Masahiro Numa, Hikaru Sebe, Ryo Matsuzuka, Osamu Maida, Daisuke Kanemoto, Tetsuya Hirose

Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020

2019

Sub-0.1V Input, Low-Voltage CMOS Driver Circuit for Multi-Stage Switched Capacitor Voltage Boost Converter.

Masaya Nishi, Yuichiro Nakazawa, Kaori Matsumoto, Nobutaka Kuroki, Masahiro Numa, Ryo Matsuzuka, Osamu Maida, Daisuke Kanemoto, Tetsuya Hirose

Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

Applying Outlier Detection and Independent Component Analysis for Compressed Sensing EEG Measurement Framework.

Shun Katsumata, Daisuke Kanemoto, Makoto Ohki

Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019

2018

Framework of Applying Independent Component Analysis After Compressed Sensing for Electroencephalogram Signals.

Daisuke Kanemoto, Shun Katsumata, Masao Aihara, Makoto Ohki

Proceedings of the 2018 IEEE Biomedical Circuits and Systems Conference, 2018

2015

Effect of Linearity Enhancement in A/D Conversion for Single Carrier Transmission Systems.

Osamu Muta, Daisuke Kanemoto, Syota Fukushige, Hiroshi Furukawa

Proceedings of the IEEE 81st Vehicular Technology Conference, 2015

A tri-level 50MS/s 10-bit capacitive-DAC for Bluetooth applications.

Daisuke Kanemoto, Keigo Oshiro, Keiji Yoshida, Haruichi Kanaya

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

A design methodology for SAR ADC optimal redundancy bit.

Toru Okazaki, Daisuke Kanemoto, Ramesh K. Pokharel, Keiji Yoshida, Haruichi Kanaya

IEICE Electron. Express, 2014

High frequency ring oscillator using capacitor based level shift circuits.

Takahide Sato, Takeshi Nagata, Daisuke Kanemoto

Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013

A self-biasing class-E power amplifier for 5-GHz constant envelope modulation system.

Yuki Yamashita, Daisuke Kanemoto, Haruichi Kanaya, Ramesh K. Pokharel, Keiji Yoshida

IEICE Electron. Express, 2013

2012

A High Dynamic Range and Low Power Consumption Audio Delta-Sigma Modulator with Opamp Sharing Technique among Three Integrators.

Daisuke Kanemoto, Toru Ido, Kenji Taniguchi

IEICE Trans. Electron., 2012

A novel RC time constant tuning technique utilizing programmable current sources for continuous-time delta-sigma modulators.

Daisuke Kanemoto, Yu Tamura, Indika U. K. Bogoda Appuhamylage, Toshimasa Matsuoka, Kenji Taniguchi

IEICE Electron. Express, 2012

A novel high-precision DAC utilizing tribonacci series.

Kazuya Hokazono, Daisuke Kanemoto, Haruichi Kanaya, Ramesh K. Pokharel, Keiji Yoshida

IEICE Electron. Express, 2012

A small die area and high linearity 10-bit capacitive three-level DAC.

Keigo Oshiro, Daisuke Kanemoto, Haruichi Kanaya, Ramesh K. Pokharel, Keiji Yoshida

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011

A third order delta-sigma modulator employing shared opamp technique for WCDMA on 0.18um CMOS.

Ghazal A. Fahmy, Daisuke Kanemoto, Haruichi Kanaya, Keiji Yoshida, Ramesh K. Pokharel, Awinash Anand

IEICE Electron. Express, 2011

A Novel 100ppm/°C current reference for ultra-low-power subthreshold applications.

Indika U. K. Bogoda Appuhamylage, Daisuke Kanemoto, Kenji Taniguchi

IEICE Electron. Express, 2011

A 7.5mW 101dB SNR low-power high-performance audio delta-sigma modulator utilizing opamp sharing technique.

Daisuke Kanemoto, Toru Ido, Kenji Taniguchi

Proceedings of the International SoC Design Conference, 2011

2008

A novel third order Delta Sigma Modulator with one opamp shared among three integrator stages.

Daisuke Kanemoto, Toru Ido, Kenji Taniguchi

IEICE Electron. Express, 2008