Darshit Vaghani

According to our database, Darshit Vaghani authored at least 8 papers between 2016 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2018

On Securing Scan Design Through Test Vector Encryption.

Darshit Vaghani, Satyadev Ahlawat, Jaynarayan T. Tudu, Masahiro Fujita, Virendra Singh

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Using MISR as Countermeasure Against Scan-Based Side-Channel Attacks.

Satyadev Ahlawat, Darshit Vaghani, Naveen Bazard, Virendra Singh

Proceedings of the 2018 IEEE East-West Design & Test Symposium, 2018

2017

A Cost Effective Technique for Diagnosis of Scan Chain Faults.

Satyadev Ahlawat, Darshit Vaghani, Jaynarayan T. Tudu, Ashok Suhag

Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

A low cost technique for scan chain diagnosis.

Satyadev Ahlawat, Darshit Vaghani, Rohini Gulve, Virendra Singh

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

An efficient test technique to prevent scan-based side-channel attacks.

Satyadev Ahlawat, Darshit Vaghani, Virendra Singh

Proceedings of the 22nd IEEE European Test Symposium, 2017

Preventing scan-based side-channel attacks through key masking.

Satyadev Ahlawat, Darshit Vaghani, Virendra Singh

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

On Securing Scan Design from Scan-Based Side-Channel Attacks.

Satyadev Ahlawat, Darshit Vaghani, Jaynarayan T. Tudu, Virendra Singh

Proceedings of the 26th IEEE Asian Test Symposium, 2017

2016

Enabling LOS delay test with slow scan enable.

Satyadev Ahlawat, Darshit Vaghani, Rohini Gulve, Virendra Singh

Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016