Rohini Gulve

According to our database1, Rohini Gulve authored at least 10 papers between 2016 and 2018.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2018
ATPG power guards: On limiting the test power below threshold.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
On Testing of Superscalar Processors in Functional Mode for Delay Faults.
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

On Generation of Delay Test with Capture Power Safety.
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

Multi-mode Toggle Random Access Scan to Minimize Test Application Time.
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

A low cost technique for scan chain diagnosis.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Instruction-based self-test for delay faults maximizing operating temperature.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

PHP: Power hungry pattern generation at higher abstraction level.
Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017

2016
On determination of instantaneous peak and cycle peak switching using ILP.
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

ILP based don't care bits filling technique for reducing capture power.
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016

Enabling LOS delay test with slow scan enable.
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016


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