Deanna Postles Dunn Berger

According to our database, Deanna Postles Dunn Berger authored at least 6 papers between 2015 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

Enterprise Class On-Chip Accelerator Integration.

Deanna Postles Dunn Berger, Alper Buyuktosunoglu, Craig R. Walters, Robert J. Sonnelitter, Hailey Nicholson, Ashraf ElSharif, Yamil Rivera, Avery Francois, Cédric Lichtenau, Jason Kohl

Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2026

2025

Enterprise Class Modular Cache Hierarchy.

Craig R. Walters, Deanna Postles Dunn Berger, Robert J. Sonnelitter, Alper Buyuktosunoglu

Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2025

2024

Enterprise-Class Cache Compression Design.

Alper Buyuktosunoglu, David Trilla, Bülent Abali, Deanna Postles Dunn Berger, Craig R. Walters, Jang-Soo Lee

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024

2023

Enterprise-Class Multilevel Cache Design: Low Latency, Huge Capacity, and High Reliability.

Deanna Postles Dunn Berger, Christian Jacobi, Craig R. Walters, Robert J. Sonnelitter, Mike Cadigan, Matthias Klein

IEEE Micro, 2023

2020

Design of the IBM z15 microprocessor.

Anthony Saporito, Martin Recktenwald, Christian Jacobi, Gerrit Koch, Deanna Postles Dunn Berger, Robert J. Sonnelitter, Craig R. Walters, Jang-Soo Lee, Cédric Lichtenau, Ulrich Mayer, Eduard Herkel, Stefan Payer, Silvia M. Müller, Vesselina K. Papazova, Ekaterina M. Ambroladze, Timothy C. Bronson

IBM J. Res. Dev., 2020

2015

The IBM z13 processor cache subsystem.

Craig R. Walters, Pak-kin Mak, Deanna Postles Dunn Berger, Michael A. Blake, Tim Bronson, K. D. Klapproth, A. J. O'Neill, Robert J. Sonnelitter, Vesselina K. Papazova

IBM J. Res. Dev., 2015