Silvia M. Müller
According to our database1,
Silvia M. Müller
authored at least 44 papers
between 1988 and 2023.
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Bibliography
2023
Proceedings of the 33rd Annual International Conference on Computer Science and Software Engineering, 2023
2022
A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling.
IEEE J. Solid State Circuits, 2022
HERMES-Core - A 1.59-TOPS/mm<sup>2</sup> PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs.
IEEE J. Solid State Circuits, 2022
A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference.
CoRR, 2022
2021
HERMES Core - A 14nm CMOS and PCM-based In-Memory Compute Core using an array of 300ps/LSB Linearized CCO-based ADCs and local digital processing.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021
2020
A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
Proceedings of the CASCON '20: Proceedings of the 30th Annual International Conference on Computer Science and Software Engineering, Toronto, Ontario, Canada, November 10, 2020
2019
DLFloat: A 16-b Floating Point Format Designed for Deep Learning Training and Inference.
Proceedings of the 26th IEEE Symposium on Computer Arithmetic, 2019
2018
A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
Proceedings of the International Symposium on Low Power Electronics and Design, 2018
2016
Proceedings of the 23nd IEEE Symposium on Computer Arithmetic, 2016
2014
Lecture Notes in Computer Science 9000, Springer, ISBN: 978-3-319-13906-7, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2011
Proceedings of the 20th IEEE Symposium on Computer Arithmetic, 2011
Proceedings of the 20th IEEE Symposium on Computer Arithmetic, 2011
2009
Proceedings of the 19th IEEE Symposium on Computer Arithmetic, 2009
2007
Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI.
IBM J. Res. Dev., 2007
2006
A fully pipelined single-precision floating-point unit in the synergistic processor element of a CELL processor.
IEEE J. Solid State Circuits, 2006
IEEE J. Solid State Circuits, 2006
2005
The Vector Floating-Point Unit in a Synergistic Processor Element of a CELL Processor.
Proceedings of the 17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 2005
Proceedings of the 17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 2005
2000
Proving the Correctness of Pipelined Micro-Architectures.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Frankfurt, Germany, February 28, 2000
Proceedings of the Euro-Par 2000, Parallel Processing, 6th International Euro-Par Conference, Munich, Germany, August 29, 2000
Springer, ISBN: 978-3-540-67481-8, 2000
1999
Proceedings of the Eleventh Annual ACM Symposium on Parallel Algorithms and Architectures, 1999
The Impact of Hardware Scheduling Mechanismus on the Performance and Cost of Processor Designs.
Proceedings of the Architektur von Rechensystemen, Systemarchitektur auf dem Weg ins 3. Jahrtausend: Neue Strukturen, Konzepte, Verfahren und Bewertungsmethoden, 1999
A Hardware Scheduler for Controlling Variable Latency Functional Units.
Proceedings of the 17th IASTED International Conference on Applied Informatics, 1999
1998
J. Circuits Syst. Comput., 1998
1997
Proceedings of the 11th International Parallel Processing Symposium (IPPS '97), 1997
1996
Making the Original Scoreboard Mechanism Deadlock Free.
Proceedings of the Fourth Israel Symposium on Theory of Computing and Systems, 1996
1995
Lecture Notes in Computer Science 995, Springer, ISBN: 3-540-60580-0, 1995
1994
Efficient mapping of randomly sparse neural networks on parallel vector supercomputers.
Proceedings of the Sixth IEEE Symposium on Parallel and Distributed Processing, 1994
Isolating the Reasons for the Performance of Parallel Machines on Numerical Programs.
Proceedings of the Automatic Parallelization: New Approaches to Code Generation, 1994
1991
1989
Contributions of Theoretical Computer Science, Applied Computer Science and Numerical Mathematics to the Design of Parallel Computers.
Proceedings of the Information Processing 89, Proceedings of the IFIP 11th World Computer Congress, San Francisco, USA, August 28, 1989
1988
Proceedings of the Innovative Informations-Infrastrukturen, 1988