David Trilla

Orcid: 0000-0001-9402-7703

According to our database1, David Trilla authored at least 15 papers between 2016 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024

Enterprise-Class Cache Compression Design.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024

2021
Worst-Case Energy Consumption: A New Challenge for Battery-Powered Critical Devices.
IEEE Trans. Sustain. Comput., 2021

NOVIA: A Framework for Discovering Non-Conventional Inline Accelerators.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

SafeTI: a Hardware Traffic Injector for MPSoC Functional and Timing Validation.
Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021

SafeDE: a flexible Diversity Enforcement hardware module for light-lockstepping.
Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021

SafeSU: an Extended Statistics Unit for Multicore Timing Interference.
Proceedings of the 26th IEEE European Test Symposium, 2021

2020
Non-functional considerations of time-randomized processor architectures.
PhD thesis, 2020

2019
Randomization for Safer, more Reliable and Secure, High-Performance Automotive Processors.
IEEE Des. Test, 2019

Modeling the Impact of Process Variations in Worst-Case Energy Consumption Estimation.
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

An Approach for Detecting Power Peaks During Testing and Breaking Systematic Pathological Behavior.
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

2018
Cache side-channel attacks and time-predictability in high-performance critical real-time systems.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
Modelling bus contention during system early design stages.
Proceedings of the 12th IEEE International Symposium on Industrial Embedded Systems, 2017

2016
Improving Early Design Stage Timing Modeling in Multicore Based Real-Time Systems.
Proceedings of the 2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), 2016

Resilient random modulo cache memories for probabilistically-analyzable real-time systems.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016


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