Debajit Bhattacharya

According to our database, Debajit Bhattacharya authored at least 7 papers between 2013 and 2017.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2017

Analytical Modeling of the SMART NoC.

Debajit Bhattacharya, Niraj K. Jha

IEEE Trans. Multi Scale Comput. Syst., 2017

2016

TCAD-Assisted Capacitance Extraction of FinFET SRAM and Logic Arrays.

Debajit Bhattacharya, Niraj K. Jha

IEEE Trans. Very Large Scale Integr. Syst., 2016

Ultra-High Density Monolithic 3-D FinFET SRAM With Enhanced Read Stability.

Debajit Bhattacharya, Niraj K. Jha

IEEE Trans. Circuits Syst. I Regul. Pap., 2016

Fast FinFET Device Simulation under Process-Voltage Variations Using an Assisted Speed-Up Mechanism.

Sourindra Chaudhuri, Ajay N. Bhoj, Debajit Bhattacharya, Niraj K. Jha

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

2015

Design of Efficient Content Addressable Memories in High-Performance FinFET Technology.

Debajit Bhattacharya, Ajay N. Bhoj, Niraj K. Jha

IEEE Trans. Very Large Scale Integr. Syst., 2015

2014

TCAD structure synthesis and capacitance extraction of a voltage-controlled oscillator using automated layout-to-device synthesis methodology.

Debajit Bhattacharya, Rajiv V. Joshi, Herschel A. Ainspan, Ninad D. Sathaye, Mohit Bajaj, Suresh Gundapaneni, Niraj K. Jha

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013

Design and Implementation of a High-Speed, Power-Efficient, Modified Hybrid-Mode Sense Amplifier for SRAM Applications.

Debajit Bhattacharya, Ashis Maity, Amit Patra

Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013