Herschel A. Ainspan

According to our database1, Herschel A. Ainspan authored at least 35 papers between 1995 and 2020.

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Bibliography

2020
A 250-mW 60-GHz CMOS Transceiver SoC Integrated With a Four-Element AiP Providing Broad Angular Link Coverage.
IEEE J. Solid State Circuits, 2020

Errata Erratum to "A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS".
IEEE J. Solid State Circuits, 2020

A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS.
IEEE J. Solid State Circuits, 2020

A Monolithically Integrated Silicon Photonics 8×8 Switch in 90nm SOI CMOS.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

An 8×8 Silicon Photonic Switch Module with Nanosecond-Scale Reconfigurability.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2020

2019
Toward Optical Networks using Rapid Amplified Multi-Wavelength Photonic Switches.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2019


A 128Gb/s 1.3pJ/b PAM-4 Transmitter with Reconfigurable 3-Tap FFE in 14nm CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018
A 32 Gb/s, 4.7 pJ/bit Optical Link With -11.7 dBm Sensitivity in 14-nm FinFET CMOS.
IEEE J. Solid State Circuits, 2018

FEC-Free 60-Gb/s Silicon Photonic Link Using SiGe-Driver ICs Hybrid-Integrated with Photonics-Enabled CMOS.
Proceedings of the Optical Fiber Communications Conference and Exposition, 2018

2017
6.5 A 1.8pJ/b 56Gb/s PAM-4 transmitter with fractionally spaced FFE in 14nm CMOS.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016
A 1.8 pJ/bit 16×16Gb/s Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration.
IEEE J. Solid State Circuits, 2016

10.8 A 12-to-26GHz fractional-N PLL with dual continuous tuning LC-D/VCOs.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015
A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology.
IEEE J. Solid State Circuits, 2015

14nm FinFET based supply voltage boosting techniques for extreme low Vmin operation.
Proceedings of the Symposium on VLSI Circuits, 2015

10.9 A 13.1-to-28GHz fractional-N PLL in 32nm SOI CMOS with a ΔΣ noise-cancellation scheme.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014
A 28 GHz Hybrid PLL in 32 nm SOI CMOS.
IEEE J. Solid State Circuits, 2014

Functional block extraction for hardware security detection using time-integrated and time-resolved emission measurements.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

TCAD structure synthesis and capacitance extraction of a voltage-controlled oscillator using automated layout-to-device synthesis methodology.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2012
An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects.
IEEE J. Solid State Circuits, 2012

A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology.
IEEE J. Solid State Circuits, 2012

A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2009
Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008
Experimental Analysis of Substrate Noise Effect on PLL Performance.
IEEE Trans. Circuits Syst. II Express Briefs, 2008

A Modular All-Digital PLL Architecture Enabling Both 1-to-2GHz and 24-to-32GHz Operation in 65nm CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007
An Ultra-Compact Differentially Tuned 6-GHz CMOS LC-VCO With Dynamic Common-Mode Feedback.
IEEE J. Solid State Circuits, 2007

2006
A 10Gb/s 5-Tap-DFE/4-Tap-FFE Transceiver in 90nm CMOS.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2003
A direct-conversion receiver integrated circuit for WCDMA mobile systems.
IBM J. Res. Dev., 2003

SiGe BiCMOS integrated circuits for high-speed serial communication links.
IBM J. Res. Dev., 2003

1995
Performance of fiber-optic data links using 670-nm cw VCSELs and a monolithic Si photodetector and CMOS preamplifier.
IBM J. Res. Dev., 1995

CMOS circuits for Gb/s serial data communication.
IBM J. Res. Dev., 1995

A 1.6-Gb/s CMOS Phase-Frequency Locked Loop for Timing Recovery.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995


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