Herschel A. Ainspan

According to our database, Herschel A. Ainspan authored at least 48 papers between 1995 and 2022.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of four.

2022

An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS.

Serdar S. Yonar, Pier Andrea Francese, Matthias Brändli, Marcel A. Kossel, Thomas Morf, Jonathan E. Proesel, Sergey V. Rylov, Herschel A. Ainspan, Martin Cochet, Zeynep Toprak Deniz, Timothy O. Dickson, Troy J. Beukema, Christian W. Baks, Michael P. Beakes, John F. Bulzacchelli, Young-Ho Choi, Byoung-Joo Yoo, Hyoungbae Ahn, Dong-Hyuk Lim, Gunil Kang, Sang-Hune Park, Mounir Meghelli, Hyo-Gyuem Rhew, Daniel J. Friedman, Michael Choi, Mehmet Soyuer, Jongshin Shin

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2020

A 250-mW 60-GHz CMOS Transceiver SoC Integrated With a Four-Element AiP Providing Broad Angular Link Coverage.

Bodhisatwa Sadhu, Alberto Valdes-Garcia, Jean-Olivier Plouchart, Herschel A. Ainspan, Arpit K. Gupta, Mark A. Ferriss, Mark Yeck, Mihai Sanduleanu, Xiaoxiong Gu, Christian W. Baks, Duixian Liu, Daniel J. Friedman

IEEE J. Solid State Circuits, 2020

Errata Erratum to "A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS".

Zeynep Toprak Deniz, Jonathan E. Proesel, John F. Bulzacchelli, Herschel A. Ainspan, Timothy O. Dickson, Michael P. Beakes, Mounir Meghelli

IEEE J. Solid State Circuits, 2020

A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS.

Zeynep Toprak Deniz, Jonathan E. Proesel, John F. Bulzacchelli, Herschel A. Ainspan, Timothy O. Dickson, Michael P. Beakes, Mounir Meghelli

IEEE J. Solid State Circuits, 2020

A Monolithically Integrated Silicon Photonics 8×8 Switch in 90nm SOI CMOS.

Jonathan E. Proesel, Nicolas Dupuis, Herschel A. Ainspan, Christian W. Baks, Fuad E. Doany, Nicolas Boyer, Elaine Cyr, Benjamin G. Lee

Proceedings of the IEEE Symposium on VLSI Circuits, 2020

An 8×8 Silicon Photonic Switch Module with Nanosecond-Scale Reconfigurability.

Nicolas Dupuis, Jonathan E. Proesel, Nicolas Boyer, Herschel A. Ainspan, Christian W. Baks, Fuad E. Doany, Elaine Cyr, Benjamin G. Lee

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2020

2019

Toward Optical Networks using Rapid Amplified Multi-Wavelength Photonic Switches.

Benjamin G. Lee, Nicolas Dupuis, Fuad E. Doany, Laurent Schares, Nicolas Boyer, Nathalie Normand, Herschel A. Ainspan, Christian W. Baks, Jonathan E. Proesel, Isabel De Sousa, Mounir Meghelli, Marc A. Taubenblatt

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2019

Multi-Wavelength Optical Transceivers Integrated on Node (MOTION).

Daniel M. Kuchta, Jonathan E. Proesel, Fuad E. Doany, Wooram Lee, Timothy O. Dickson, Herschel A. Ainspan, Mounir Meghelli, Petar K. Pepeljugoski, Xiaoxiong Gu, Michael P. Beakes, Mark Schultz, Marc Taubenblatt, Paul Fortier, Catherine Dufort, Éric Turcotte, Marc-Olivier Pion, Charles Bureau, Frank Flens, Greta Light, Blake Trekell, Kevin Koski

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2019

A 128Gb/s 1.3pJ/b PAM-4 Transmitter with Reconfigurable 3-Tap FFE in 14nm CMOS.

Zeynep Toprak Deniz, Jonathan E. Proesel, John F. Bulzacchelli, Herschel A. Ainspan, Timothy O. Dickson, Michael P. Beakes, Mounir Meghelli

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018

A 32 Gb/s, 4.7 pJ/bit Optical Link With -11.7 dBm Sensitivity in 14-nm FinFET CMOS.

Jonathan E. Proesel, Zeynep Toprak Deniz, Alessandro Cevrero, Ilter Özkaya, Seongwon Kim, Daniel M. Kuchta, Sungjae Lee, Sergey V. Rylov, Herschel A. Ainspan, Timothy O. Dickson, John F. Bulzacchelli, Mounir Meghelli

IEEE J. Solid State Circuits, 2018

FEC-Free 60-Gb/s Silicon Photonic Link Using SiGe-Driver ICs Hybrid-Integrated with Photonics-Enabled CMOS.

Benjamin G. Lee, Nicolas Dupuis, Jason Orcutt, Javier Ayala, Karen Nummy, Herschel A. Ainspan, Jonathan E. Proesel, Christian W. Baks, Douglas M. Gill, Mounir Meghelli, William M. J. Green

Proceedings of the Optical Fiber Communications Conference and Exposition, 2018

2017

6.5 A 1.8pJ/b 56Gb/s PAM-4 transmitter with fractionally spaced FFE in 14nm CMOS.

Timothy O. Dickson, Herschel A. Ainspan, Mounir Meghelli

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016

A 1.8 pJ/bit 16×16Gb/s Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration.

Timothy O. Dickson, Yong Liu, Ankur Agrawal, John F. Bulzacchelli, Herschel A. Ainspan, Zeynep Toprak Deniz, Benjamin D. Parker, Michael P. Beakes, Mounir Meghelli, Daniel J. Friedman

IEEE J. Solid State Circuits, 2016

10.8 A 12-to-26GHz fractional-N PLL with dual continuous tuning LC-D/VCOs.

Mark A. Ferriss, Bodhisatwa Sadhu, Alexander V. Rylyakov, Herschel A. Ainspan, Daniel J. Friedman

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015

A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology.

Timothy O. Dickson, Yong Liu, Sergey V. Rylov, Ankur Agrawal, Seongwon Kim, Ping-Hsuan Hsieh, John F. Bulzacchelli, Mark A. Ferriss, Herschel A. Ainspan, Alexander V. Rylyakov, Benjamin D. Parker, Michael P. Beakes, Christian W. Baks, Lei Shan, Young Hoon Kwark, José A. Tierno, Daniel J. Friedman

IEEE J. Solid State Circuits, 2015

14nm FinFET based supply voltage boosting techniques for extreme low Vmin operation.

Rajiv V. Joshi, Matthew M. Ziegler, Holger Wetter, C. Wandel, Herschel A. Ainspan

Proceedings of the Symposium on VLSI Circuits, 2015

10.9 A 13.1-to-28GHz fractional-N PLL in 32nm SOI CMOS with a ΔΣ noise-cancellation scheme.

Mark A. Ferriss, Bodhisatwa Sadhu, Alexander V. Rylyakov, Herschel A. Ainspan, Daniel J. Friedman

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration.

Timothy O. Dickson, Yong Liu, Ankur Agrawal, John F. Bulzacchelli, Herschel A. Ainspan, Zeynep Toprak Deniz, Benjamin D. Parker, Mounir Meghelli, Daniel J. Friedman

Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014

A 28 GHz Hybrid PLL in 32 nm SOI CMOS.

Mark A. Ferriss, Alexander V. Rylyakov, José A. Tierno, Herschel A. Ainspan, Daniel J. Friedman

IEEE J. Solid State Circuits, 2014

Functional block extraction for hardware security detection using time-integrated and time-resolved emission measurements.

Franco Stellari, Peilin Song, Herschel A. Ainspan

Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology.

Timothy O. Dickson, Yong Liu, Sergey V. Rylov, Ankur Agrawal, Seongwon Kim, Ping-Hsuan Hsieh, John F. Bulzacchelli, Mark A. Ferriss, Herschel A. Ainspan, Alexander V. Rylyakov, Benjamin D. Parker, Christian W. Baks, Lei Shan, Young Hoon Kwark, José A. Tierno, Daniel J. Friedman

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

TCAD structure synthesis and capacitance extraction of a voltage-controlled oscillator using automated layout-to-device synthesis methodology.

Debajit Bhattacharya, Rajiv V. Joshi, Herschel A. Ainspan, Ninad D. Sathaye, Mohit Bajaj, Suresh Gundapaneni, Niraj K. Jha

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2012

An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects.

Timothy O. Dickson, Yong Liu, Sergey V. Rylov, Bing Dang, Cornelia K. Tsang, Paul S. Andry, John F. Bulzacchelli, Herschel A. Ainspan, Xiaoxiong Gu, Lavanya Turlapati, Michael P. Beakes, Benjamin D. Parker, John U. Knickerbocker, Daniel J. Friedman

IEEE J. Solid State Circuits, 2012

A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology.

John F. Bulzacchelli, Christian Menolfi, Troy J. Beukema, Daniel W. Storaska, Juergen Hertle, David Hanson, Ping-Hsuan Hsieh, Sergey V. Rylov, Daniel Furrer, Daniele Gardellini, Andrea Prati, Thomas Morf, Vivek Sharma, Ram Kelkar, Herschel A. Ainspan, W. R. Kelly, L. R. Chieco, Glenn Ritter, J. A. Sorice, Jon Garlett, Robert Callan, Matthias Braendli, Peter Buchmann, Marcel A. Kossel, Thomas Toifl, Daniel J. Friedman

IEEE J. Solid State Circuits, 2012

A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology.

John F. Bulzacchelli, Troy J. Beukema, Daniel W. Storaska, Ping-Hsuan Hsieh, Sergey V. Rylov, Daniel Furrer, Daniele Gardellini, Andrea Prati, Christian Menolfi, David Hanson, Juergen Hertle, Thomas Morf, Vivek Sharma, Ram Kelkar, Herschel A. Ainspan, William Kelly, Glenn Ritter, Jon Garlett, Robert Callan, Thomas Toifl, Daniel J. Friedman

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2009

Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications.

Alexander V. Rylyakov, José A. Tierno, Herschel A. Ainspan, Jean-Olivier Plouchart, John F. Bulzacchelli, Zeynep Toprak Deniz, Daniel J. Friedman

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS.

John F. Bulzacchelli, Timothy O. Dickson, Zeynep Toprak Deniz, Herschel A. Ainspan, Benjamin D. Parker, Michael P. Beakes, Sergey V. Rylov, Daniel J. Friedman

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008

Experimental Analysis of Substrate Noise Effect on PLL Performance.

Woogeun Rhee, Keith A. Jenkins, John C. Liobe, Herschel A. Ainspan

IEEE Trans. Circuits Syst. II Express Briefs, 2008

A Modular All-Digital PLL Architecture Enabling Both 1-to-2GHz and 24-to-32GHz Operation in 65nm CMOS.

Alexander V. Rylyakov, José A. Tierno, Didem Zeliha Turker, Jean-Olivier Plouchart, Herschel A. Ainspan, Daniel J. Friedman

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007

An Ultra-Compact Differentially Tuned 6-GHz CMOS LC-VCO With Dynamic Common-Mode Feedback.

Babak Soltanian, Herschel A. Ainspan, Woogeun Rhee, Daniel J. Friedman, Peter R. Kinget

IEEE J. Solid State Circuits, 2007

2006

A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology.

John F. Bulzacchelli, Mounir Meghelli, Sergey V. Rylov, Woogeun Rhee, Alexander V. Rylyakov, Herschel A. Ainspan, Benjamin D. Parker, Michael P. Beakes, Aichin Chung, Troy J. Beukema, Petar K. Pepeljugoski, Lei Shan, Young Hoon Kwark, Sudhir M. Gowda, Daniel J. Friedman

IEEE J. Solid State Circuits, 2006

A 10Gb/s 5-Tap-DFE/4-Tap-FFE Transceiver in 90nm CMOS.

Mounir Meghelli, Sergey V. Rylov, John F. Bulzacchelli, Woogeun Rhee, Alexander V. Rylyakov, Herschel A. Ainspan, Benjamin D. Parker, Michael P. Beakes, Aichin Chung, Troy J. Beukema, Petar K. Pepeljugoski, L. Shan, Young Hoon Kwark, Sudhir M. Gowda, Daniel J. Friedman

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005

A 6.4-Gb/s CMOS SerDes core with feed-forward and decision-feedback equalization.

Troy J. Beukema, Michael Sorna, Karl Selander, Steven Zier, Brian L. Ji, Phil Murfet, James Mason, Woogeun Rhee, Herschel A. Ainspan, Benjamin D. Parker, Michael P. Beakes

IEEE J. Solid State Circuits, 2005

2003

A direct-conversion receiver IC for WCDMA mobile systems.

Scott K. Reynolds, Brian A. Floyd, Troy J. Beukema, Thomas Zwick, Ullrich R. Pfeiffer, Herschel A. Ainspan

IEEE J. Solid State Circuits, 2003

A direct-conversion receiver integrated circuit for WCDMA mobile systems.

Scott K. Reynolds, Brian A. Floyd, Troy J. Beukema, Thomas Zwick, Ullrich R. Pfeiffer, Herschel A. Ainspan

IBM J. Res. Dev., 2003

SiGe BiCMOS integrated circuits for high-speed serial communication links.

Daniel J. Friedman, Mounir Meghelli, Benjamin D. Parker, Jungwook Yang, Herschel A. Ainspan, Alexander V. Rylyakov, Young Hoon Kwark, Mark B. Ritter, Lei Shan, Steven J. Zier, Michael Sorna, Mehmet Soyuer

IBM J. Res. Dev., 2003

A 10-Gb/s CMOS clock and data recovery circuit using a secondary delay-locked loop.

Woogeun Rhee, Herschel A. Ainspan, Sergey V. Rylov, Alexander V. Rylyakov, Michael P. Beakes, Daniel J. Friedman, Sudhir M. Gowda, Mehmet Soyuer

Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

2000

Low-power multi-GHz and multi-Gb/s SiGe BiCMOS circuits.

Mehmet Soyuer, Herschel A. Ainspan, Mounir Meghelli, Jean-Olivier Plouchart

Proc. IEEE, 2000

SiGe BiCMOS 3.3-V clock and data recovery circuits for 10-Gb/s serial transmission systems.

Mounir Meghelli, Benjamin D. Parker, Herschel A. Ainspan, Mehmet Soyuer

IEEE J. Solid State Circuits, 2000

1999

A 5.2 GHz 3.3 V I/Q SiGe RF transceiver.

Jean-Olivier Plouchart, Herschel A. Ainspan, Mehmet Soyuer

Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999

1998

A 3.3-V, 500-Mb/s/ch parallel optical receiver in 1.2-μm GaAs technology.

Jungwook Yang, Joongho Choi, Daniel M. Kuchta, Kevin G. Stawiasz, Petar K. Pepeljugoski, Herschel A. Ainspan

IEEE J. Solid State Circuits, 1998

RF circuit design aspects of spiral inductors on silicon.

Joachim N. Burghartz, Daniel C. Edelstein, Mehmet Soyuer, Herschel A. Ainspan, Keith A. Jenkins

IEEE J. Solid State Circuits, 1998

1997

An 11 GHz 3-V SiGe voltage controlled oscillator with integrated resonator.

Mehmet Soyuer, Joachim N. Burghartz, Herschel A. Ainspan, Keith A. Jenkins, Peter Xiao, Arvin R. Shahani, Margaret S. Dolan, David L. Harame

IEEE J. Solid State Circuits, 1997

1996

Single-chip 4×500-MBd CMOS transceiver.

Albert X. Widmer, Kevin R. Wrenner, Herschel A. Ainspan, Ben Parker, Pierre Austruy, Bernard Brezzo, Anne-Marie Haen, John F. Ewen, Mehmet Soyuer, Alain Blanc, Jean-Claude Abbiate, Alina Deutsch, Hyun J. Shin

IEEE J. Solid State Circuits, 1996

A 2.4-GHz silicon bipolar oscillator with integrated resonator.

Mehmet Soyuer, Keith A. Jenkins, Joachim N. Burghartz, Herschel A. Ainspan, Frank J. Canora, Slaila Ponnapalli, John F. Ewen, William E. Pence

IEEE J. Solid State Circuits, 1996

1995

Performance of fiber-optic data links using 670-nm cw VCSELs and a monolithic Si photodetector and CMOS preamplifier.

Daniel M. Kuchta, Herschel A. Ainspan, Frank J. Canora, Richard P. Schneider Jr.

IBM J. Res. Dev., 1995

CMOS circuits for Gb/s serial data communication.

John F. Ewen, Mehmet Soyuer, Albert X. Widmer, Kevin R. Wrenner, Benjamin D. Parker, Herschel A. Ainspan

IBM J. Res. Dev., 1995

A 1.6-Gb/s CMOS Phase-Frequency Locked Loop for Timing Recovery.

Mehmet Soyuer, Herschel A. Ainspan, John F. Ewen

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995