Niraj K. Jha

According to our database1, Niraj K. Jha authored at least 411 papers between 1985 and 2019.

Collaborative distances:

Awards

ACM Fellow

ACM Fellow 2003, "For contributions to low power design and testing of digital systems.".

IEEE Fellow

IEEE Fellow 1998, "For contributions to high-level design and synthesis of testable VLSI circuits.".

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

Homepages:

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Bibliography

2019
Three-Dimensional Monolithic FinFET-Based 8T SRAM Cell Design for Enhanced Read Time and Low Leakage.
IEEE Trans. VLSI Syst., 2019

NeST: A Neural Network Synthesis Tool Based on a Grow-and-Prune Paradigm.
IEEE Trans. Computers, 2019

SPRING: A Sparsity-Aware Reduced-Precision Monolithic 3D CNN Accelerator Architecture for Training and Inference.
CoRR, 2019

SECRET: Semantically Enhanced Classification of Real-world Tasks.
CoRR, 2019

Incremental Learning Using a Grow-and-Prune Paradigm with Efficient Neural Networks.
CoRR, 2019

SCANN: Synthesis of Compact and Accurate Neural Networks.
CoRR, 2019

Software-Defined Design Space Exploration for an Efficient AI Accelerator Architecture.
CoRR, 2019

Hardware-Guided Symbiotic Training for Compact, Accurate, yet Execution-Efficient LSTM.
CoRR, 2019

2018
Hybrid Monolithic 3-D IC Floorplanner.
IEEE Trans. VLSI Syst., 2018

A Monolithic 3D Hybrid Architecture for Energy-Efficient Computation.
IEEE Trans. Multi-Scale Computing Systems, 2018

A Hierarchical Inference Model for Internet-of-Things.
IEEE Trans. Multi-Scale Computing Systems, 2018

OpSecure: A Secure Unidirectional Optical Channel for Implantable Medical Devices.
IEEE Trans. Multi-Scale Computing Systems, 2018

PinMe: Tracking a Smartphone User around the World.
IEEE Trans. Multi-Scale Computing Systems, 2018

Smart, Secure, Yet Energy-Efficient, Internet-of-Things Sensors.
IEEE Trans. Multi-Scale Computing Systems, 2018

Genetic Programming for Energy-Efficient and Energy-Scalable Approximate Feature Computation in Embedded Inference Systems.
IEEE Trans. Computers, 2018

Statistical Optimization of FinFET Processor Architectures under PVT Variations Using Dual Device-Type Assignment.
JETC, 2018

Smart Healthcare.
Foundations and Trends in Electronic Design Automation, 2018

ChamNet: Towards Efficient Network Design through Platform-Aware Model Adaptation.
CoRR, 2018

Grow and Prune Compact, Fast, and Accurate LSTMs.
CoRR, 2018

PinMe: Tracking a Smartphone User around the World.
CoRR, 2018

Detecting and Alleviating Stress with SoDA.
IEEE Computer, 2018

Smart Health Care: An Edge-Side Computing Perspective.
IEEE Consumer Electronics Magazine, 2018

Keynotes.
Proceedings of the IEEE International Conference on Consumer Electronics, 2018

Smart healthcare.
Proceedings of the IEEE International Conference on Consumer Electronics, 2018

Simultaneously ensuring smartness, security, and energy efficiency in Internet-of-Things sensors.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

2017
Using a Device State Library to Boost the Performance of TCAD Mixed-Mode Simulation.
IEEE Trans. VLSI Syst., 2017

Improving Convergence and Simulation Time of Quantum Hydrodynamic Simulation: Application to Extraction of Best 10-nm FinFET Parameter Values.
IEEE Trans. VLSI Syst., 2017

A Health Decision Support System for Disease Diagnosis Based on Wearable Medical Sensors and Machine Learning Ensembles.
IEEE Trans. Multi-Scale Computing Systems, 2017

DISASTER: Dedicated Intelligent Security Attacks on Sensor-Triggered Emergency Responses.
IEEE Trans. Multi-Scale Computing Systems, 2017

Wearable Medical Sensor-Based System Design: A Survey.
IEEE Trans. Multi-Scale Computing Systems, 2017

Analytical Modeling of the SMART NoC.
IEEE Trans. Multi-Scale Computing Systems, 2017

Keep the Stress Away with SoDA: Stress Detection and Alleviation System.
IEEE Trans. Multi-Scale Computing Systems, 2017

A Comprehensive Study of Security of Internet-of-Things.
IEEE Trans. Emerging Topics Comput., 2017

CABA: Continuous Authentication Based on BioAura.
IEEE Trans. Computers, 2017

Automated Quantum Circuit Synthesis and Cost Estimation for the Binary Welded Tree Oracle.
JETC, 2017

NeST: A Neural Network Synthesis Tool Based on a Grow-and-Prune Paradigm.
CoRR, 2017

Internet-of-Medical-Things.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

2016
GenFin: Genetic Algorithm-Based Multiobjective Statistical Logic Circuit Optimization Using Incremental Statistical Analysis.
IEEE Trans. VLSI Syst., 2016

Reducing Wire and Energy Overheads of the SMART NoC Using a Setup Request Network.
IEEE Trans. VLSI Syst., 2016

A 3-D CPU-FPGA-DRAM Hybrid Architecture for Low-Power Computation.
IEEE Trans. VLSI Syst., 2016

TCAD-Assisted Capacitance Extraction of FinFET SRAM and Logic Arrays.
IEEE Trans. VLSI Syst., 2016

Physiological Information Leakage: A New Frontier in Health Information Security.
IEEE Trans. Emerging Topics Comput., 2016

Ultra-High Density Monolithic 3-D FinFET SRAM With Enhanced Read Stability.
IEEE Trans. on Circuits and Systems, 2016

Compressed Signal Processing on Nyquist-Sampled Signals.
IEEE Trans. Computers, 2016

Delay/Power Modeling and Optimization of FinFET Circuit Modules under PVT Variations: Observing the Trends between the 22nm and 14nm Technology Nodes.
JETC, 2016

Ultra-low-leakage, Robust FinFET SRAM Design Using Multiparameter Asymmetric FinFETs.
JETC, 2016

Ultra-Low-Leakage and High-Performance Logic Circuit Design Using Multiparameter Asymmetric FinFETs.
JETC, 2016

Fast FinFET Device Simulation under Process-Voltage Variations Using an Assisted Speed-Up Mechanism.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

2015
McPAT-PVT: Delay and Power Modeling Framework for FinFET Processor Architectures Under PVT Variations.
IEEE Trans. VLSI Syst., 2015

Signal Processing With Direct Computations on Compressively Sensed Data.
IEEE Trans. VLSI Syst., 2015

FDR 2.0: A Low-Power Dynamically Reconfigurable Architecture and Its FinFET Implementation.
IEEE Trans. VLSI Syst., 2015

PAQCS: Physical Design-Aware Fault-Tolerant Quantum Circuit Synthesis.
IEEE Trans. VLSI Syst., 2015

Design of Efficient Content Addressable Memories in High-Performance FinFET Technology.
IEEE Trans. VLSI Syst., 2015

Energy-Efficient Long-term Continuous Personal Health Monitoring.
IEEE Trans. Multi-Scale Computing Systems, 2015

Systematic Poisoning Attacks on and Defenses for Machine Learning in Healthcare.
IEEE J. Biomedical and Health Informatics, 2015

gem5-PVT: A Framework for FinFET System Simulation under PVT Variations.
JETC, 2015

Synthesis of Quantum Circuits for Dedicated Physical Machine Descriptions.
Proceedings of the Reversible Computation - 7th International Conference, 2015

Vibration-based secure side channel for medical devices.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
FinPrin: FinFET Logic Circuit Analysis and Optimization Under PVT Variations.
IEEE Trans. VLSI Syst., 2014

A Fine-Grain Dynamically Reconfigurable Architecture Aimed at Reducing the FPGA-ASIC Gaps.
IEEE Trans. VLSI Syst., 2014

FTQLS: Fault-Tolerant Quantum Logic Synthesis.
IEEE Trans. VLSI Syst., 2014

FinCANON: A PVT-Aware Integrated Delay and Power Modeling Framework for FinFET-Based Caches and On-Chip Networks.
IEEE Trans. VLSI Syst., 2014

Parasitics-Aware Design of Symmetric and Asymmetric Gate-Workfunction FinFET SRAMs.
IEEE Trans. VLSI Syst., 2014

A 0.6-107 µW Energy-Scalable Processor for Directly Analyzing Compressively-Sensed EEG.
IEEE Trans. on Circuits and Systems, 2014

Trustworthiness of Medical Devices and Body Area Networks.
Proceedings of the IEEE, 2014

RMDDS: Reed-muller decision diagram synthesis of reversible logic circuits.
JETC, 2014

QLib: Quantum module library.
JETC, 2014

Ultra-low-leakage chip multiprocessor design with hybrid FinFET logic styles.
JETC, 2014

Accurate Leakage/Delay Estimation for FinFET Standard Cells under PVT Variations using the Response Surface Methodology.
JETC, 2014

3D vs. 2D Device Simulation of FinFET Logic Gates under PVT Variations.
JETC, 2014

A defense framework against malware and vulnerability exploits.
Int. J. Inf. Sec., 2014

FinFET Logic Circuit Optimization with Different FinFET Styles: Lower Power Possible at Higher Supply Voltage.
Proceedings of the 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, 2014

TCAD structure synthesis and capacitance extraction of a voltage-controlled oscillator using automated layout-to-device synthesis methodology.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013
Algorithm-Driven Architectural Design Space Exploration of Domain-Specific Medical-Sensor Processors.
IEEE Trans. VLSI Syst., 2013

Optimized Quantum Gate Library for Various Physical Machine Descriptions.
IEEE Trans. VLSI Syst., 2013

Variable-Pipeline-Stage Router.
IEEE Trans. VLSI Syst., 2013

3-D-TCAD-Based Parasitic Capacitance Extraction for Emerging Multigate Devices and Circuits.
IEEE Trans. VLSI Syst., 2013

Design of Logic Gates and Flip-Flops in High-Performance FinFET Technology.
IEEE Trans. VLSI Syst., 2013

Efficient Methodologies for 3-D TCAD Modeling of Emerging Devices and Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

MedMon: Securing Medical Devices Through Wireless Monitoring and Anomaly Detection.
IEEE Trans. Biomed. Circuits and Systems, 2013

Design space exploration of FinFET cache.
JETC, 2013

Thermal Characterization of Test Techniques for FinFET and 3D Integrated Circuits.
JETC, 2013

Improving the Trustworthiness of Medical Device Software with Formal Verification Methods.
Embedded Systems Letters, 2013

Energy-efficient and Secure Sensor Data Transmission Using Encompression.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

Fin Prin: Analysis and Optimization of FinFET Logic Circuits under PVT Variations.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

Embedded Reconfigurable Augmented DC-DC Boost Converter for Fast Transient Recovery.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

Emerging Frontiers in Embedded Security.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

Localized Heating for Building Energy Efficiency.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

Towards trustworthy medical devices and body area networks.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012
SRAM-Based NATURE: A Dynamically Reconfigurable FPGA Based on 10T Low-Power SRAMs.
IEEE Trans. VLSI Syst., 2012

A Trusted Virtual Machine in an Untrusted Management Environment.
IEEE Trans. Services Computing, 2012

Secure reconfiguration of software-defined radio.
ACM Trans. Embedded Comput. Syst., 2012

INVISIOS: A Lightweight, Minimally Intrusive Secure Execution Environment.
ACM Trans. Embedded Comput. Syst., 2012

Accurate Leakage Estimation for FinFET Standard Cells Using the Response Surface Methodology.
Proceedings of the 25th International Conference on VLSI Design, 2012

Design of Quantum Circuits for Random Walk Algorithms.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Enabling advanced inference on sensor nodes through direct use of compressively-sensed signals.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

A compressed-domain processor for seizure detection to simultaneously reduce computation and communication energy.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011
Editorial Announcing a New Editor-in-Chief.
IEEE Trans. VLSI Syst., 2011

A framework for defending embedded systems against software attacks.
ACM Trans. Embedded Comput. Syst., 2011

FinFET-Based Power Management for Improved DPA Resistance with Low Overhead.
JETC, 2011

Design of ultra-low-leakage logic gates and flip-flops in high-performance FinFET technology.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

3D vs. 2D analysis of FinFET logic gates under process variations.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

A low-energy computation platform for data-driven biomedical monitoring algorithms.
Proceedings of the 48th Design Automation Conference, 2011

CACTI-FinFET: an integrated delay and power modeling framework for FinFET-based caches under process variations.
Proceedings of the 48th Design Automation Conference, 2011

2010
Editorial: New Associate Editor Appointments.
IEEE Trans. VLSI Syst., 2010

Low-power 3D nano/CMOS hybrid dynamically reconfigurable architecture.
JETC, 2010

FinFET-based power simulator for interconnection networks.
JETC, 2010

Gated-diode FinFET DRAMs: Device and circuit design-considerations.
JETC, 2010

NanoV: Nanowire-based VLSI design.
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, 2010

Fault modeling for FinFET circuits.
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, 2010

Die-level leakage power analysis of FinFET circuits considering process variations.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Low-power FinFET circuit synthesis using surface orientation optimization.
Proceedings of the Design, Automation and Test in Europe, 2010

Secure Virtual Machine Execution under an Untrusted Management OS.
Proceedings of the IEEE International Conference on Cloud Computing, 2010

A Secure User Interface for Web Applications Running Under an Untrusted Operating System.
Proceedings of the 10th IEEE International Conference on Computer and Information Technology, 2010

2009
Fast Enhancement of Validation Test Sets for Improving the Stuck-at Fault Coverage of RTL Circuits.
IEEE Trans. VLSI Syst., 2009

Editorial Appointments for the 2009-2010 Term.
IEEE Trans. VLSI Syst., 2009

Design space exploration and data memory architecture design for a hybrid nano/CMOS dynamically reconfigurable architecture.
JETC, 2009

A hybrid nano/CMOS dynamically reconfigurable system - Part I: Architecture.
JETC, 2009

A hybrid Nano/CMOS dynamically reconfigurable system - Part II: Design optimization flow.
JETC, 2009

A hybrid nano-CMOS architecture for defect and fault tolerance.
JETC, 2009

Low-power FinFET circuit synthesis using multiple supply and threshold voltages.
JETC, 2009

In-network coherence filtering: snoopy coherence without broadcasts.
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009

Thermal characterization of BIST, scan design and sequential test methodologies.
Proceedings of the 2009 IEEE International Test Conference, 2009

GARNET: A detailed on-chip network model inside a full-system simulator.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2009

FinFET-based dynamic power management of on-chip interconnection networks through adaptive back-gate biasing.
Proceedings of the 27th International Conference on Computer Design, 2009

Pragmatic design of gated-diode FinFET DRAMs.
Proceedings of the 27th International Conference on Computer Design, 2009

In-Network Snoop Ordering (INSO): Snoopy coherence on unordered interconnects.
Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009

An architecture for secure software defined radio.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Automatic Test Generation for Combinational Threshold Logic Networks.
IEEE Trans. VLSI Syst., 2008

An energy-aware framework for dynamic software management in mobile computing systems.
ACM Trans. Embedded Comput. Syst., 2008

Analysis and design of a hardware/software trusted platform module for embedded systems.
ACM Trans. Embedded Comput. Syst., 2008

System-Level Dynamic Thermal Management for High-Performance Microprocessors.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Toward Ideal On-Chip Communication Using Express Virtual Channels.
IEEE Micro, 2008

Reversible logic synthesis with Fredkin and Peres gates.
JETC, 2008

Fault-Tolerant Computing Using a Hybrid Nano-CMOS Architecture.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Variability-Tolerant Register-Transfer Level Synthesis.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Threshold Voltage Control through Multiple Supply Voltages for Power-Efficient FinFET Interconnects.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Evaluation of multiple supply and threshold voltages for low-power FinFET circuit synthesis.
Proceedings of the 2008 IEEE International Symposium on Nanoscale Architectures, 2008

Token flow control.
Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), 2008

A system-level perspective for efficient NoC design.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

Dynamic Binary Instrumentation-Based Framework for Malware Defense.
Proceedings of the Detection of Intrusions and Malware, 2008

2007
Configuration and Extension of Embedded Processors to Optimize IPSec Protocol Execution.
IEEE Trans. VLSI Syst., 2007

Aiding Side-Channel Attacks on Cryptographic Software With Satisfiability-Based Analysis.
IEEE Trans. VLSI Syst., 2007

Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems.
IEEE Trans. VLSI Syst., 2007

Satisfiability-Based Automatic Test Program Generation and Design for Testability for Microprocessors.
IEEE Trans. VLSI Syst., 2007

Editorial.
IEEE Trans. VLSI Syst., 2007

Generation of Heterogeneous Distributed Architectures for Memory-Intensive Applications Through High-Level Synthesis.
IEEE Trans. VLSI Syst., 2007

A Test Generation Framework for Quantum Cellular Automata Circuits.
IEEE Trans. VLSI Syst., 2007

Exploring Software Partitions for Fast Security Processing on a Multiprocessor Mobile SoC.
IEEE Trans. VLSI Syst., 2007

Architectural Support for Run-Time Validation of Program Data Properties.
IEEE Trans. VLSI Syst., 2007

Hybrid Architectures for Efficient and Secure Face Authentication in Embedded Systems.
IEEE Trans. VLSI Syst., 2007

Energy-optimizing source code transformations for operating system-driven embedded software.
ACM Trans. Embedded Comput. Syst., 2007

Majority and Minority Network Synthesis With Application to QCA-, SET-, and TPL-Based Nanotechnologies.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

A Synthesis Methodology for Hybrid Custom Instruction and Coprocessor Generation for Extensible Processors.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

SLOPES: Hardware-Software Cosynthesis of Low-Power Real-Time Distributed Embedded Systems With Dynamically Reconfigurable FPGAs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Hybrid Simulation for Energy Estimation of Embedded Software.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Automated Energy/Performance Macromodeling of Embedded Software.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Power-Efficient Scheduling for Heterogeneous Distributed Real-Time Embedded Systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Efficient Design for Testability Solution Based on Unsatisfiability for Register-Transfer Level Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Fast Enhancement of Validation Test Sets to Improve Stuck-at Fault Coverage for RTL circuits.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Express virtual channels: towards the ideal interconnection fabric.
Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007

CMOS logic design with independent-gate FinFETs.
Proceedings of the 25th International Conference on Computer Design, 2007

A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS.
Proceedings of the 25th International Conference on Computer Design, 2007

Energy and execution time analysis of a software-based trusted platform module.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

NanoMap: An Integrated Design Optimization Flow for a Hybrid Nanotube/CMOS Dynamically Reconfigurable Architecture.
Proceedings of the 44th Design Automation Conference, 2007

Energy comparison and optimization of wireless body-area network technologies.
Proceedings of the 2nd International ICST Conference on Body Area Networks, 2007

2006
A Scalable Synthesis Methodology for Application-Specific Processors.
IEEE Trans. VLSI Syst., 2006

Hardware-Assisted Run-Time Monitoring for Secure Program Execution on Embedded Processors.
IEEE Trans. VLSI Syst., 2006

Dynamic Power Optimization Targeting User Delays in Interactive Systems.
IEEE Trans. Mob. Comput., 2006

Energy-Efficient Graphical User Interface Design.
IEEE Trans. Mob. Comput., 2006

A Study of the Energy Consumption Characteristics of Cryptographic Algorithms and Security Protocols.
IEEE Trans. Mob. Comput., 2006

RTL-Aware Cycle-Accurate Functional Power Estimation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Application-specific heterogeneous multiprocessor synthesis using extensible processors.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

PowerHerd: a distributed scheme for dynamically satisfying peak-power constraints in interconnection networks.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Satisfiability-based test generation for nonseparable RTL controller-datapath circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Use of Computation-Unit Integrated Memories in High-Level Synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

An Algorithm for Synthesis of Reversible Logic Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Temperature-Aware On-Chip Networks.
IEEE Micro, 2006

State Encoding of Finite-State Machines Targeting Threshold and Majority Logic Based Implementations with Application to Nanotechnologies.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Hybrid Custom Instruction and Co-Processor Synthesis Methodology for Extensible Processors.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Impact of Configurability and Extensibility on IPSec Protocol Execution on Embedded Processors.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Improving the Performance of Automatic Sequential Test Generation by Targeting Hard-to-Test Faults.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Active Learning Driven Data Acquisition for Sensor Networks.
Proceedings of the 11th IEEE Symposium on Computers and Communications (ISCC 2006), 2006

Threshold/majority logic synthesis and concurrent error detection targeting nanoelectronic implementations.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

Satisfiability-based framework for enabling side-channel attacks on cryptographic software.
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

Test generation for combinational quantum cellular automata (QCA) circuits.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Architectures for efficient face authentication in embedded systems.
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture.
Proceedings of the 43rd Design Automation Conference, 2006

HybDTM: a coordinated hardware-software approach for dynamic thermal management.
Proceedings of the 43rd Design Automation Conference, 2006

Software architecture exploration for high-performance security processing on a multiprocessor mobile SoC.
Proceedings of the 43rd Design Automation Conference, 2006

Architectural support for safe software execution on embedded processors.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

2005
Memory binding for performance optimization of control-flow intensive behavioral descriptions.
IEEE Trans. VLSI Syst., 2005

Energy macromodeling of embedded operating systems.
ACM Trans. Embedded Comput. Syst., 2005

Interconnect-aware low-power high-level synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

Threshold network synthesis and optimization and its application to nanotechnologies.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

Joint dynamic voltage scaling and adaptive body biasing for heterogeneous distributed real-time embedded systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

Input space-adaptive optimization for embedded-software synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

Generation of distributed logic-memory architectures through high-level synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

Integrated functional partitioning and synthesis for low power distributed systems of systems-on-a-chip.
IJES, 2005

Unsatisfiability Based Efficient Design for Testability Solution for Register-Transfer Level Circuits.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Synthesis of Majority and Minority Networks and Its Applications to QCA, TPL and SET Based Nanotechnologies.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Synthesis of Application-Specific Heterogeneous Multiprocessor Architectures Using Extensible Processors.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Heterogeneous and Multi-Level Compression Techniques for Test Volume Reduction in Systems-on-Chip.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Energy efficiency of handheld computer interfaces: limits, characterization and practice.
Proceedings of the 3rd International Conference on Mobile Systems, 2005

A personal-area network of low-power wireless interfacing devices for handhelds: system and hardware design.
Proceedings of the 7th Conference on Human-Computer Interaction with Mobile Devices and Services, 2005

Towards a Responsive, Yet Power-ef.cient, Operating System: A Holistic Approach.
Proceedings of the 13th International Symposium on Modeling, 2005

ALLCN: An Automatic Logic-to-Layout Tool for Carbon Nanotube Based Nanotechnology.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Nanotechnology in the Service of Embedded and Ubiquitous Computing.
Proceedings of the Embedded and Ubiquitous Computing, 2005

Secure Embedded Processing through Hardware-Assisted Run-Time Monitoring.
Proceedings of the 2005 Design, 2005

User-perceived latency driven voltage scaling for interactive applications.
Proceedings of the 42nd Design Automation Conference, 2005

Hybrid simulation for embedded software energy estimation.
Proceedings of the 42nd Design Automation Conference, 2005

Efficient fingerprint-based user authentication for embedded systems.
Proceedings of the 42nd Design Automation Conference, 2005

Enhancing security through hardware-assisted run-time validation of program data properties.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

Eliminating memory bottlenecks for a JPEG encoder through distributed logic-memory architecture and computation-unit integrated memory.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004
Input space adaptive design: a high-level methodology for optimizing energy and performance.
IEEE Trans. VLSI Syst., 2004

DESP: A Distributed Economics-Based Subcontracting Protocol for Computation Distribution in Power-Aware Mobile Ad Hoc Networks.
IEEE Trans. Mob. Comput., 2004

Resource budgeting for Multiprocess High-level synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

Custom-instruction synthesis for extensible-processor platforms.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

Register binding-based RTL power management for control-flow intensive designs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

Common-case computation: a high-level energy and performance optimization technique.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

A hybrid energy-estimation technique for extensible processors.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

COWLS: hardware-software cosynthesis of wireless low-power distributed embedded client-server systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

Dynamic Power Optimization of Interactive Systems.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Profiling Driven Computation Reuse: An Embedded Software Synthesis Technique for Energy and Performance Optimization.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Energy-Optimizing Source Code Transformations for OS-driven Embedded Software.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Thermal Modeling, Characterization and Management of On-Chip Networks.
Proceedings of the 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 2004

An Energy-Aware Framework for Coordinated Dynamic Software Management in Mobile Computers.
Proceedings of the 12th International Workshop on Modeling, 2004

Energy-Efficient Graphical User Interface Design.
Proceedings of the International Conference on Wireless Networks, 2004

An Automatic Test Pattern Generation Framework for Combinational Threshold Logic Networks.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Power estimation for cycle-accurate functional descriptions of hardware.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

High-level synthesis using computation-unit integrated memories.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies.
Proceedings of the 2004 Design, 2004

An Algorithm for Nano-Pipelining of Circuits and Architectures for a Nanotechnology.
Proceedings of the 2004 Design, 2004

Synthesis of Reversible Logic.
Proceedings of the 2004 Design, 2004

Automated energy/performance macromodeling of embedded software.
Proceedings of the 41th Design Automation Conference, 2004

Language Selection for Mobile Systems: Java, C, or Both?
Proceedings of the International Conference on Embedded Systems and Applications, 2004

Evaluating Conditional Statements in Embedded System Software: Systematic Methodologies for Reducing Energy Consumption.
Proceedings of the International Conference on Embedded Systems and Applications, 2004

An Energy-Aware Synthesis Methodology for OS-Driven Multi-Process Embedded Software.
Proceedings of the International Conference on Embedded Systems and Applications, 2004

2003
High-level macro-modeling and estimation techniques for switching activity and power consumption.
IEEE Trans. VLSI Syst., 2003

A simulation framework for energy-consumption analysis of OS-driven embedded applications.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

Analysis of power dissipation in embedded systems using real-time operating systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

High-level Synthesis of Multi-process Behavioral Descriptions.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Task Graph Extraction for Embedded System Synthesis.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Power-profile Driven Variable Voltage Sealing for Heterogeneous Distributed Real-time Embedded Systems.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Analyzing the energy consumption of security protocols.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

PowerHerd: dynamic satisfaction of peak power constraints in interconnection networks.
Proceedings of the 17th Annual International Conference on Supercomputing, 2003

Test Generation for Non-separable RTL Controller-datapath Circuits using a Satisfiability based Approach.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Heterogeneous Distributed Real-time Embedded Systems.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

A Scalable Application-Specific Processor Synthesis Methodology.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Synthesis of Heterogeneous Distributed Architectures for Memory-Intensive Applications.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

A High-level Interconnect Power Model for Design Space Exploration.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks.
Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), 2003

A comprehensive high-level synthesis system for control-flow intensive behaviors.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

Software Architectural Transformations: A New Approach to Low Energy Embedded Software.
Proceedings of the 2003 Design, 2003

Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems.
Proceedings of the 2003 Design, 2003

Energy Estimation for Extensible Processors.
Proceedings of the 2003 Design, 2003

Graphical user interface energy characterization for handheld computers.
Proceedings of the International Conference on Compilers, 2003

Software Architectural Transformations.
Proceedings of the Embedded Software for SoC, 2003

2002
Leakage power analysis and reduction during behavioral synthesis.
IEEE Trans. VLSI Syst., 2002

High-level energy macromodeling of embedded software.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

High-level test compaction techniques.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

Test synthesis of systems-on-a-chip.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

Power-efficient Interconnection Networks: Dynamic Voltage Scaling with Links.
Computer Architecture Letters, 2002

Input Space Adaptive Embedded Software Synthesis.
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

Hardware-Software Co-Synthesis of Low Power Real-Time Distributed Embedded Systems with Dynamically Reconfigurable FPGAs.
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

Static and Dynamic Variable Voltage Scheduling Algorithms for Real-Time Heterogeneous Distributed Embedded Systems.
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

Functional Partitioning for Low Power Distributed Systems of Systems-on-a-Chip.
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

An Economics-based Power-aware Protocol for Computation Distribution in Mobile Ad-Hoc Networks.
Proceedings of the International Conference on Parallel and Distributed Computing Systems, 2002

Task graph transformation to aid system synthesis.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Register Binding Based Power Management for High-level Synthesis of Control-Flow Intensive Behaviors.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Embedded Operating System Energy Analysis and Macro-Modeling.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Interconnect-aware high-level synthesis for low power.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Synthesis of custom processors based on extensible platforms.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

High-level synthesis of distributed logic-memory architectures.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Low Power Distributed Embedded Systems: Dynamic Voltage Scaling and Synthesis.
Proceedings of the High Performance Computing, 2002

2001
TAO: regular expression-based register-transfer level testability analysis and optimization.
IEEE Trans. VLSI Syst., 2001

Testing of core-based systems-on-a-chip.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

Fault-diagnosis-based technique for establishing RTL and gate-levelcorrespondences.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

Clock selection for performance optimization of control-flowintensive behaviors.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

Synthesis of System-on-a-chip for Testability.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Fast test generation for circuits with RTL and gate-level views.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

High-Level Power Modeling of CPLDs and FPGAs.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

Low Power System Scheduling and Synthesis.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Input Space Adaptive Design: A High-level Methodology for Energy and Performance Optimization.
Proceedings of the 38th Design Automation Conference, 2001

High-level Software Energy Macro-modeling.
Proceedings of the 38th Design Automation Conference, 2001

Battery-Aware Static Scheduling for Distributed Real-Time Embedded Systems.
Proceedings of the 38th Design Automation Conference, 2001

2000
TAO-BIST: A framework for testability analysis and optimization forbuilt-in self-test of RTL circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2000

Incorporating speculative execution into scheduling ofcontrol-flow-intensive designs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2000

A BIST scheme for RTL circuits based on symbolic testabilityanalysis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2000

A fast and low-cost testing technique for core-based system-chips.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2000

Behavioral Synthesis of Fault Secure Controller/Datapaths Based on Aliasing Probability Analysis.
IEEE Trans. Computers, 2000

Clock Selection for Performance Optimization of Control-Flow Intensive Behaviors.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

COWLS: Hardware-Software Co-Synthesis of Distributed Wireless Low-Power Embedded Client-Server Systems.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

: Reducing test application time in high-level test generation.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

A Technique for Identifying RTL and Gate-Level Correspondences.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

Leakage Power Analysis and Reduction during Behavioral Synthesis.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

Power-Conscious Joint Scheduling of Periodic Task Graphs and Aperiodic Tasks in Distributed Real-Time Embedded Systems.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Power analysis of embedded operating systems.
Proceedings of the 37th Conference on Design Automation, 2000

1999
Power management in high-level synthesis.
IEEE Trans. VLSI Syst., 1999

COSYN: Hardware-software co-synthesis of heterogeneous distributed embedded systems.
IEEE Trans. VLSI Syst., 1999

Safety and Reliability Driven Task Allocation in Distributed Systems.
IEEE Trans. Parallel Distrib. Syst., 1999

Register transfer level power optimization with emphasis on glitch analysis and reduction.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1999

Wavesched: a novel scheduling technique for control-flow intensive designs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1999

FACT: a framework for applying throughput and power optimizing transformations to control-flow-intensive behavioral descriptions.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1999

High-level synthesis of power-optimized and area-optimized circuits from hierarchical data-flow intensive behaviors.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1999

High-level synthesis of low-power control-flow intensive circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1999

Hierarchical test generation and design for testability methods for ASPPs and ASIPs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1999

A low overhead design for testability and test generation technique for core-based systems-on-a-chip.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1999

Corrections to "mogac: a multiobjective genetic algorithm for hardware-software cosynthesis of distributed embedded systems".
IEEE Trans. on CAD of Integrated Circuits and Systems, 1999

Controller-based power management for control-flow intensive designs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1999

COFTA: Hardware-Software Co-Synthesis of Heterogeneous Distributed Embedded Systems.
IEEE Trans. Computers, 1999

TAO-BIST: A Framework for Testability Analysis and Optimizationb of RTL Circuits for BIST.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

A framework for testing core-based systems-on-a-chip.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Memory binding for performance optimization of control-flow intensive behaviors.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

MOCSYN: Multiobjective Core-Based Single-Chip System Synthesis.
Proceedings of the 1999 Design, 1999

Common-Case Computation: A High-Level Technique for Power and Performance Optimization.
Proceedings of the 36th Conference on Design Automation, 1999

1998
Integration of hierarchical test generation with behavioral synthesis of controller and data path circuits.
IEEE Trans. VLSI Syst., 1998

A design-for-testability technique for register-transfer level circuits using control/data flow extraction.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1998

MOGAC: a multiobjective genetic algorithm for hardware-software cosynthesis of distributed embedded systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1998

COHRA: hardware-software cosynthesis of hierarchical heterogeneous distributed embedded systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1998

High-level test synthesis: a survey.
Integration, 1998

Guest Editorial.
J. Electronic Testing, 1998

A Power Management Methodology for High-Level Synthesis.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

COHRA: Hardware-Software Co-Synthesis of Hierarchical Distributed Embedded System Architectures.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

TAO: regular expression based high-level testability analysis and optimization.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Fast high-level power estimation for control-flow intensive design.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

Removal of memory access bottlenecks for scheduling control-flow intensive behavioral descriptions.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Transforming control-flow intensive designs to facilitate power management.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

CORDS: hardware-software co-synthesis of reconfigurable real-time distributed embedded systems.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

IMPACT: A High-Level Synthesis System for Low Power Control-Flow Intensive Circuits.
Proceedings of the 1998 Design, 1998

CASPER: Concurrent Hardware-Software Co-Synthesis of Hard Real-Time Aperiodic and Periodic Specifications of Embedded System Architectures.
Proceedings of the 1998 Design, 1998

Incorporating Speculative Execution into Scheduling of Control-Flow Intensive Behavioral Descriptions.
Proceedings of the 35th Conference on Design Automation, 1998

Synthesis of Power-Optimized and Area-Optimized Circuits from Hierarchical Behavioral Descriptions.
Proceedings of the 35th Conference on Design Automation, 1998

FACT: A Framework for the Application of Throughput and Power Optimizing Transformations to Control-Flow Intensive Behavioral Descriptions.
Proceedings of the 35th Conference on Design Automation, 1998

A BIST Scheme for RTL Controller-Data Paths Based on Symbolic Testability Analysis.
Proceedings of the 35th Conference on Design Automation, 1998

A Fast and Low Cost Testing Technique for Core-Based System-on-Chip.
Proceedings of the 35th Conference on Design Automation, 1998

High-Level Power Analysis and Optimization.
Kluwer, ISBN: 978-0-7923-8073-3, 1998

1997
Graceful Degradation in Algorithm-Based Fault Tolerant Multiprocessor Systems.
IEEE Trans. Parallel Distrib. Syst., 1997

Analysis and Randomized Design of Algorithm-Based Fault Tolerant Multiprocessor Systems Under an Extended Model.
IEEE Trans. Parallel Distrib. Syst., 1997

SCALP: an iterative-improvement-based low-power data path synthesis system.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1997

Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1997

Design for hierarchical testability of RTL circuits obtained by behavioral synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1997

A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

Wavesched: a novel scheduling technique for control-flow intensive behavioral descriptions.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

MOGAC: a multiobjective genetic algorithm for the co-synthesis of hardware-software embedded systems.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

COFTA: Hardware-Software Co-Synthesis of Heterogeneous Distributed Embedded System Architectures for Low Overhead Fault Tolerance.
Proceedings of the Digest of Papers: FTCS-27, 1997

Power Management Techniques for Control-Flow Intensive Designs.
Proceedings of the 34st Conference on Design Automation, 1997

Hierarchical Test Generation and Design for Testability of ASPPs and ASIPs.
Proceedings of the 34st Conference on Design Automation, 1997

COSYN: Hardware-Software Co-Synthesis of Embedded Systems.
Proceedings of the 34st Conference on Design Automation, 1997

1996
Synthesis for parallel scan: applications to partial scan and robust path-delay fault testability.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1996

Hardware-Software Co-Design for Test: It's the Last Straw!
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Controller re-specification to minimize switching activity in controller/data path circuits.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

Register-transfer level estimation techniques for switching activity and power consumption.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

A design for testability technique for RTL circuits using control/data flow extraction.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Behavioral Synthesis of Fault Secure Controller?Datapaths using Aliasing Probability Analysis.
Proceedings of the Digest of Papers: FTCS-26, 1996

Glitch Analysis and Reduction in Register Transfer Level.
Proceedings of the 33st Conference on Design Automation, 1996

1995
Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability.
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

An ILP Formulation for Low Power Based on Minimizing Switched Capacitance During Data Path Allocation.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Task Allocation for Safety and Reliability in Distributed Systems.
Proceedings of the 1995 International Conference on Parallel Processing, 1995

Design for hierarchical testability of RTL circuits obtained by behavioral synthesis.
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

An iterative improvement algorithm for low power data path synthesis.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Hardware-software co-synthesis of fault-tolerant real-time distributed embedded systems.
Proceedings of the Proceedings EURO-DAC'95, 1995

1994
Design of Algorithm-Based Fault-Tolerant Multiprocessor Systems for Concurrent Error Detection and Fault Diagnosis.
IEEE Trans. Parallel Distrib. Syst., 1994

Partitioned Encoding Schemes for Algorithm-Based Fault Tolerance in Massively Parallel Systems.
IEEE Trans. Parallel Distrib. Syst., 1994

Algorithm-Based Fault Tolerance for FFT Networks.
IEEE Trans. Computers, 1994

A Totally Self-Checking Checker for a Parallel Unordered Coding Scheme.
IEEE Trans. Computers, 1994

Synthesis of Fault Tolerant Architectures for Molecular Dynamics.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Graceful Degradation in Algorithm-Based Fault Tolerant Multiprocessor Systems.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Behavioral Synthesis for low Power.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

Behavioral Synthesis for Hierarchical Testability of Controller/Data Path Circuits with Conditional Branches.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

Genesis: A Behavioral Synthesis System for Hierarchical Testability.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1993
Synthesis of Algorithm-Based Fault-Tolerant Systems from Dependence Graphs.
IEEE Trans. Parallel Distrib. Syst., 1993

Design and synthesis of self-checking VLSI circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1993

Easily testable nonrestoring and restoring gate-level cellular array dividers.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1993

Diagnosability and Diagnosis of Algorithm-Based Fault-Tolerant Systems.
IEEE Trans. Computers, 1993

Optimal Design of Checks for Error Detection and Location in Fault-Tolerant Multiprocessor Systems.
IEEE Trans. Computers, 1993

Fault Detection in CVS Parity Trees with Application to Strongly Self-Checking Parity and Two-Rail Checkers.
IEEE Trans. Computers, 1993

Synthesis of Sequential Circuits for Robust Path Delay Fault Testability.
Proceedings of the Sixth International Conference on VLSI Design, 1993

A Conditional Resource-Sharing Method for Behavior Synthesis of Highly- Testable Data Paths.
Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

Design of Algorithm-Based Fault Tolerant Systems With In-System Checks.
Proceedings of the 1993 International Conference on Parallel Processing, 1993

Efficient Diagnosis in Algorithm-Based Fault Tolerant Multiprocessor Systems.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

Synthesis of Sequential Circuits for Easy Testability Through Performance-Oriented Parallel Partial Scan.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

Behavioral Synthesis of Highly Testable Data Paths under the Non-Scan and Partial Scan Environments.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992
A totally self-checking checker for a parallel unordered coding scheme.
Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

Design and Analysis of Fault-Detecting and Fault-Locating Schedules for Computation DAGs.
Proceedings of the 6th International Parallel Processing Symposium, 1992

Behavioral Synthesis for Easy Testability in Data Path Allocation.
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

Multiple Input Bridging Fault Detection in CMOS Sequential Circuits.
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

Behavioral synthesis for easy testability in data path scheduling.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

Synthesis of Multi-Level Combinational Circuits for Complete Robust Path Delay Fault Testability.
Proceedings of the Digest of Papers: FTCS-22, 1992

1991
Easily testable gate-level and DCVS multipliers.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1991

Design of robustly testable combinational logic circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1991

Totally self-checking checker designs for Bose-Lin, Bose, and Blaum codes.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1991

A new transition count method for testing of logic circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1991

Optimal Design of Checks for Error Detection and Location in Fault Tolerant Multiprocessors Systems.
Proceedings of the Fault-Tolerant Computing Systems, Tests, Diagnosis, 1991

Design and Synthesis of Self-Checking VLSI Circuits and Systems.
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

Design of Multiprocessor Systems for Concurrent Error Detection and Fault Diagnosis.
Proceedings of the 1991 International Symposium on Fault-Tolerant Computing, 1991

MACHETE: synthesis of sequential machines for easy testability.
Proceedings of the conference on European design automation, 1991

1990
Strong fault-secure and strongly self-checking domino-CMOS implementations of totally self-checking circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1990

Design of robustly testable static CMOS parity trees derived from binary decision diagrams.
Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

A dependence graph-based approach to the design of algorithm-based fault tolerant systems.
Proceedings of the 20th International Symposium on Fault-Tolerant Computing, 1990

Detection of multiple input bridging and stuck-on faults in CMOS logic circuits using current monitoring.
Proceedings of the European Design Automation Conference, 1990

1989
A totally self-checking checker for Borden's code.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1989

Separable codes for detecting unidirectional errors.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1989

Fault detection in CVS parity trees: application in SSC CVS parity and two-rail checkers.
Proceedings of the Nineteenth International Symposium on Fault-Tolerant Computing, 1989

1988
Testing for multiple faults in domino-CMOS logic circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1988

A universal test set for CMOS circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1988

Multiple Stuck-Open Fault Detection in CMOS Logic Circuits.
IEEE Trans. Computers, 1988

On the design of robust multiple fault testable CMOS combinational logic circuits.
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

1986
Detecting Multiple Faults in CMOS Circuits.
Proceedings of the Proceedings International Test Conference 1986, 1986

1985
Design of Testable CMOS Logic Circuits Under Arbitrary Delays.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1985


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