Niraj K. Jha
Orcid: 0000-0002-1539-0369Affiliations:
- Princeton University, USA
According to our database1,
Niraj K. Jha
authored at least 447 papers
between 1985 and 2024.
Collaborative distances:
Collaborative distances:
Awards
ACM Fellow
ACM Fellow 2003, "For contributions to low power design and testing of digital systems.".
IEEE Fellow
IEEE Fellow 1998, "For contributions to high-level design and synthesis of testable VLSI circuits.".
Timeline
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Online presence:
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Bibliography
2024
PAGE: Domain-Incremental Adaptation with Past-Agnostic Generative Replay for Smart Healthcare.
CoRR, 2024
Neural Slot Interpreters: Grounding Object Semantics in Emergent Slot Representations.
CoRR, 2024
2023
TransCODE: Co-Design of Transformers and Accelerators for Efficient Training and Inference.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023
SCouT: Synthetic Counterfactuals via Spatiotemporal Transformers for Actionable Healthcare.
ACM Trans. Comput. Heal., October, 2023
REPAIRS: Gaussian Mixture Model-based Completion and Optimization of Partially Specified Systems.
ACM Trans. Embed. Comput. Syst., July, 2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2023
ACM Trans. Embed. Comput. Syst., 2023
J. Artif. Intell. Res., 2023
BREATHE: Second-Order Gradients and Heteroscedastic Emulation based Design Space Exploration.
CoRR, 2023
Zero-TPrune: Zero-Shot Token Pruning through Leveraging of the Attention Graph in Pre-Trained Transformers.
CoRR, 2023
DOCTOR: A Multi-Disease Detection Continual Learning Framework Based on Wearable Medical Sensors.
CoRR, 2023
SECRETS: Subject-Efficient Clinical Randomized Controlled Trials using Synthetic Intervention.
CoRR, 2023
EdgeTran: Co-designing Transformers for Efficient Inference on Mobile Edge Platforms.
CoRR, 2023
ML-FEED: Machine Learning Framework for Efficient Exploit Detection (Extended version).
CoRR, 2023
Proceedings of the Advances in Neural Information Processing Systems 36: Annual Conference on Neural Information Processing Systems 2023, 2023
Proceedings of Cyber-Physical Systems and Internet of Things Week 2023, 2023
2022
MHDeep: Mental Health Disorder Detection System Based on Wearable Sensors and Artificial Neural Networks.
ACM Trans. Embed. Comput. Syst., November, 2022
SPRING: A Sparsity-Aware Reduced-Precision Monolithic 3D CNN Accelerator Architecture for Training and Inference.
IEEE Trans. Emerg. Top. Comput., 2022
IEEE Trans. Emerg. Top. Comput., 2022
IEEE Trans. Emerg. Top. Comput., 2022
IEEE Trans. Emerg. Top. Comput., 2022
SHARKS: Smart Hacking Approaches for RisK Scanning in Internet-of-Things and Cyber-Physical Systems Based on Machine Learning.
IEEE Trans. Emerg. Top. Comput., 2022
IEEE Trans. Emerg. Top. Comput., 2022
IEEE Trans. Emerg. Top. Comput., 2022
GRAVITAS: Graphical Reticulated Attack Vectors for Internet-of-Things Aggregate Security.
IEEE Trans. Emerg. Top. Comput., 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
CURIOUS: Efficient Neural Architecture Search Based on a Performance Predictor and Evolutionary Search.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Proceedings of the 4th IEEE International Conference on Trust, 2022
2021
YSUY: Your Smartphone Understands You - Using Machine Learning to Address Fundamental Human Needs.
IEEE Trans. Syst. Man Cybern. Syst., 2021
DiabDeep: Pervasive Diabetes Diagnosis Based on Wearable Medical Sensors and Efficient Neural Networks.
IEEE Trans. Emerg. Top. Comput., 2021
CovidDeep: SARS-CoV-2/COVID-19 Test Based on Wearable Medical Sensors and Efficient Neural Networks.
IEEE Trans. Consumer Electron., 2021
Software-Defined Design Space Exploration for an Efficient DNN Accelerator Architecture.
IEEE Trans. Computers, 2021
IEEE Trans. Computers, 2021
HW/SW Framework for Improving the Safety of Implantable and Wearable Medical Devices.
CoRR, 2021
MHDeep: Mental Health Disorder Detection System based on Body-Area and Deep Neural Networks.
CoRR, 2021
2020
McPAT-Monolithic: An Area/Power/Timing Architecture Modeling Framework for 3-D Hybrid Monolithic Multicore Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2020
CovidDeep: SARS-CoV-2/COVID-19 Test Based on Wearable Medical Sensors and Efficient Neural Networks.
CoRR, 2020
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
Proceedings of the 2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2020
2019
Three-Dimensional Monolithic FinFET-Based 8T SRAM Cell Design for Enhanced Read Time and Low Leakage.
IEEE Trans. Very Large Scale Integr. Syst., 2019
IEEE Trans. Computers, 2019
STEERAGE: Synthesis of Neural Networks Using Architecture Search and Grow-and-Prune Methods.
CoRR, 2019
Software-Defined Design Space Exploration for an Efficient AI Accelerator Architecture.
CoRR, 2019
Hardware-Guided Symbiotic Training for Compact, Accurate, yet Execution-Efficient LSTM.
CoRR, 2019
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2019
2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Trans. Multi Scale Comput. Syst., 2018
IEEE Trans. Multi Scale Comput. Syst., 2018
IEEE Trans. Multi Scale Comput. Syst., 2018
IEEE Trans. Multi Scale Comput. Syst., 2018
IEEE Trans. Multi Scale Comput. Syst., 2018
Genetic Programming for Energy-Efficient and Energy-Scalable Approximate Feature Computation in Embedded Inference Systems.
IEEE Trans. Computers, 2018
Statistical Optimization of FinFET Processor Architectures under PVT Variations Using Dual Device-Type Assignment.
ACM J. Emerg. Technol. Comput. Syst., 2018
IEEE Consumer Electron. Mag., 2018
Proceedings of the IEEE International Conference on Consumer Electronics, 2018
Simultaneously ensuring smartness, security, and energy efficiency in Internet-of-Things sensors.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
Improving Convergence and Simulation Time of Quantum Hydrodynamic Simulation: Application to Extraction of Best 10-nm FinFET Parameter Values.
IEEE Trans. Very Large Scale Integr. Syst., 2017
A Health Decision Support System for Disease Diagnosis Based on Wearable Medical Sensors and Machine Learning Ensembles.
IEEE Trans. Multi Scale Comput. Syst., 2017
DISASTER: Dedicated Intelligent Security Attacks on Sensor-Triggered Emergency Responses.
IEEE Trans. Multi Scale Comput. Syst., 2017
IEEE Trans. Multi Scale Comput. Syst., 2017
IEEE Trans. Multi Scale Comput. Syst., 2017
IEEE Trans. Emerg. Top. Comput., 2017
Automated Quantum Circuit Synthesis and Cost Estimation for the Binary Welded Tree Oracle.
ACM J. Emerg. Technol. Comput. Syst., 2017
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
2016
GenFin: Genetic Algorithm-Based Multiobjective Statistical Logic Circuit Optimization Using Incremental Statistical Analysis.
IEEE Trans. Very Large Scale Integr. Syst., 2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
IEEE Trans. Emerg. Top. Comput., 2016
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
Delay/Power Modeling and Optimization of FinFET Circuit Modules under PVT Variations: Observing the Trends between the 22nm and 14nm Technology Nodes.
ACM J. Emerg. Technol. Comput. Syst., 2016
Ultra-low-leakage, Robust FinFET SRAM Design Using Multiparameter Asymmetric FinFETs.
ACM J. Emerg. Technol. Comput. Syst., 2016
Ultra-Low-Leakage and High-Performance Logic Circuit Design Using Multiparameter Asymmetric FinFETs.
ACM J. Emerg. Technol. Comput. Syst., 2016
Fast FinFET Device Simulation under Process-Voltage Variations Using an Assisted Speed-Up Mechanism.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
2015
McPAT-PVT: Delay and Power Modeling Framework for FinFET Processor Architectures Under PVT Variations.
IEEE Trans. Very Large Scale Integr. Syst., 2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
FDR 2.0: A Low-Power Dynamically Reconfigurable Architecture and Its FinFET Implementation.
IEEE Trans. Very Large Scale Integr. Syst., 2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
Design of Efficient Content Addressable Memories in High-Performance FinFET Technology.
IEEE Trans. Very Large Scale Integr. Syst., 2015
IEEE Trans. Multi Scale Comput. Syst., 2015
IEEE J. Biomed. Health Informatics, 2015
ACM J. Emerg. Technol. Comput. Syst., 2015
Proceedings of the Reversible Computation - 7th International Conference, 2015
Proceedings of the 52nd Annual Design Automation Conference, 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
A Fine-Grain Dynamically Reconfigurable Architecture Aimed at Reducing the FPGA-ASIC Gaps.
IEEE Trans. Very Large Scale Integr. Syst., 2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
FinCANON: A PVT-Aware Integrated Delay and Power Modeling Framework for FinFET-Based Caches and On-Chip Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
A 0.6-107 µW Energy-Scalable Processor for Directly Analyzing Compressively-Sensed EEG.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
ACM J. Emerg. Technol. Comput. Syst., 2014
ACM J. Emerg. Technol. Comput. Syst., 2014
Accurate Leakage/Delay Estimation for FinFET Standard Cells under PVT Variations using the Response Surface Methodology.
ACM J. Emerg. Technol. Comput. Syst., 2014
ACM J. Emerg. Technol. Comput. Syst., 2014
Int. J. Inf. Sec., 2014
FinFET Logic Circuit Optimization with Different FinFET Styles: Lower Power Possible at Higher Supply Voltage.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014
TCAD structure synthesis and capacitance extraction of a voltage-controlled oscillator using automated layout-to-device synthesis methodology.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
2013
Algorithm-Driven Architectural Design Space Exploration of Domain-Specific Medical-Sensor Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
3-D-TCAD-Based Parasitic Capacitance Extraction for Emerging Multigate Devices and Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
IEEE Trans. Biomed. Circuits Syst., 2013
ACM J. Emerg. Technol. Comput. Syst., 2013
Improving the Trustworthiness of Medical Device Software with Formal Verification Methods.
IEEE Embed. Syst. Lett., 2013
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
2012
IEEE Trans. Very Large Scale Integr. Syst., 2012
IEEE Trans. Serv. Comput., 2012
ACM Trans. Embed. Comput. Syst., 2012
ACM Trans. Embed. Comput. Syst., 2012
Accurate Leakage Estimation for FinFET Standard Cells Using the Response Surface Methodology.
Proceedings of the 25th International Conference on VLSI Design, 2012
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012
Enabling advanced inference on sensor nodes through direct use of compressively-sensed signals.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
A compressed-domain processor for seizure detection to simultaneously reduce computation and communication energy.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
ACM Trans. Embed. Comput. Syst., 2011
ACM J. Emerg. Technol. Comput. Syst., 2011
Design of ultra-low-leakage logic gates and flip-flops in high-performance FinFET technology.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
Proceedings of the IEEE 29th International Conference on Computer Design, 2011
Proceedings of the 48th Design Automation Conference, 2011
CACTI-FinFET: an integrated delay and power modeling framework for FinFET-based caches under process variations.
Proceedings of the 48th Design Automation Conference, 2011
2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
ACM J. Emerg. Technol. Comput. Syst., 2010
ACM J. Emerg. Technol. Comput. Syst., 2010
ACM J. Emerg. Technol. Comput. Syst., 2010
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, 2010
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, 2010
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
Proceedings of the Design, Automation and Test in Europe, 2010
Proceedings of the IEEE International Conference on Cloud Computing, 2010
A Secure User Interface for Web Applications Running Under an Untrusted Operating System.
Proceedings of the 10th IEEE International Conference on Computer and Information Technology, 2010
2009
Fast Enhancement of Validation Test Sets for Improving the Stuck-at Fault Coverage of RTL Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
Design space exploration and data memory architecture design for a hybrid nano/CMOS dynamically reconfigurable architecture.
ACM J. Emerg. Technol. Comput. Syst., 2009
ACM J. Emerg. Technol. Comput. Syst., 2009
A hybrid Nano/CMOS dynamically reconfigurable system - Part II: Design optimization flow.
ACM J. Emerg. Technol. Comput. Syst., 2009
ACM J. Emerg. Technol. Comput. Syst., 2009
ACM J. Emerg. Technol. Comput. Syst., 2009
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009
Proceedings of the 2009 IEEE International Test Conference, 2009
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2009
FinFET-based dynamic power management of on-chip interconnection networks through adaptive back-gate biasing.
Proceedings of the 27th International Conference on Computer Design, 2009
Proceedings of the 27th International Conference on Computer Design, 2009
Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009
Proceedings of the Design, Automation and Test in Europe, 2009
2008
IEEE Trans. Very Large Scale Integr. Syst., 2008
An energy-aware framework for dynamic software management in mobile computing systems.
ACM Trans. Embed. Comput. Syst., 2008
Analysis and design of a hardware/software trusted platform module for embedded systems.
ACM Trans. Embed. Comput. Syst., 2008
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
ACM J. Emerg. Technol. Comput. Syst., 2008
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
Threshold Voltage Control through Multiple Supply Voltages for Power-Efficient FinFET Interconnects.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
Evaluation of multiple supply and threshold voltages for low-power FinFET circuit synthesis.
Proceedings of the 2008 IEEE International Symposium on Nanoscale Architectures, 2008
Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), 2008
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008
Proceedings of the Detection of Intrusions and Malware, 2008
2007
Configuration and Extension of Embedded Processors to Optimize IPSec Protocol Execution.
IEEE Trans. Very Large Scale Integr. Syst., 2007
Aiding Side-Channel Attacks on Cryptographic Software With Satisfiability-Based Analysis.
IEEE Trans. Very Large Scale Integr. Syst., 2007
Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2007
Satisfiability-Based Automatic Test Program Generation and Design for Testability for Microprocessors.
IEEE Trans. Very Large Scale Integr. Syst., 2007
Generation of Heterogeneous Distributed Architectures for Memory-Intensive Applications Through High-Level Synthesis.
IEEE Trans. Very Large Scale Integr. Syst., 2007
IEEE Trans. Very Large Scale Integr. Syst., 2007
Exploring Software Partitions for Fast Security Processing on a Multiprocessor Mobile SoC.
IEEE Trans. Very Large Scale Integr. Syst., 2007
IEEE Trans. Very Large Scale Integr. Syst., 2007
Hybrid Architectures for Efficient and Secure Face Authentication in Embedded Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2007
Energy-optimizing source code transformations for operating system-driven embedded software.
ACM Trans. Embed. Comput. Syst., 2007
Majority and Minority Network Synthesis With Application to QCA-, SET-, and TPL-Based Nanotechnologies.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
A Synthesis Methodology for Hybrid Custom Instruction and Coprocessor Generation for Extensible Processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
SLOPES: Hardware-Software Cosynthesis of Low-Power Real-Time Distributed Embedded Systems With Dynamically Reconfigurable FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
Efficient Design for Testability Solution Based on Unsatisfiability for Register-Transfer Level Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
Fast Enhancement of Validation Test Sets to Improve Stuck-at Fault Coverage for RTL circuits.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007
Proceedings of the 25th International Conference on Computer Design, 2007
A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS.
Proceedings of the 25th International Conference on Computer Design, 2007
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
NanoMap: An Integrated Design Optimization Flow for a Hybrid Nanotube/CMOS Dynamically Reconfigurable Architecture.
Proceedings of the 44th Design Automation Conference, 2007
Proceedings of the 2nd International ICST Conference on Body Area Networks, 2007
2006
IEEE Trans. Very Large Scale Integr. Syst., 2006
Hardware-Assisted Run-Time Monitoring for Secure Program Execution on Embedded Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2006
IEEE Trans. Mob. Comput., 2006
A Study of the Energy Consumption Characteristics of Cryptographic Algorithms and Security Protocols.
IEEE Trans. Mob. Comput., 2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
Application-specific heterogeneous multiprocessor synthesis using extensible processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
PowerHerd: a distributed scheme for dynamically satisfying peak-power constraints in interconnection networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
Satisfiability-based test generation for nonseparable RTL controller-datapath circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
State Encoding of Finite-State Machines Targeting Threshold and Majority Logic Based Implementations with Application to Nanotechnologies.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006
Hybrid Custom Instruction and Co-Processor Synthesis Methodology for Extensible Processors.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006
Impact of Configurability and Extensibility on IPSec Protocol Execution on Embedded Processors.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006
Improving the Performance of Automatic Sequential Test Generation by Targeting Hard-to-Test Faults.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006
Proceedings of the 11th IEEE Symposium on Computers and Communications (ISCC 2006), 2006
Threshold/majority logic synthesis and concurrent error detection targeting nanoelectronic implementations.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006
Satisfiability-based framework for enabling side-channel attacks on cryptographic software.
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006
Proceedings of the 43rd Design Automation Conference, 2006
Proceedings of the 43rd Design Automation Conference, 2006
Software architecture exploration for high-performance security processing on a multiprocessor mobile SoC.
Proceedings of the 43rd Design Automation Conference, 2006
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006
2005
Memory binding for performance optimization of control-flow intensive behavioral descriptions.
IEEE Trans. Very Large Scale Integr. Syst., 2005
ACM Trans. Embed. Comput. Syst., 2005
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
Threshold network synthesis and optimization and its application to nanotechnologies.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
Joint dynamic voltage scaling and adaptive body biasing for heterogeneous distributed real-time embedded systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
Integrated functional partitioning and synthesis for low power distributed systems of systems-on-a-chip.
Int. J. Embed. Syst., 2005
Unsatisfiability Based Efficient Design for Testability Solution for Register-Transfer Level Circuits.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005
Synthesis of Majority and Minority Networks and Its Applications to QCA, TPL and SET Based Nanotechnologies.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005
Synthesis of Application-Specific Heterogeneous Multiprocessor Architectures Using Extensible Processors.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005
Heterogeneous and Multi-Level Compression Techniques for Test Volume Reduction in Systems-on-Chip.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005
Energy efficiency of handheld computer interfaces: limits, characterization and practice.
Proceedings of the 3rd International Conference on Mobile Systems, 2005
A personal-area network of low-power wireless interfacing devices for handhelds: system and hardware design.
Proceedings of the 7th Conference on Human-Computer Interaction with Mobile Devices and Services, 2005
Proceedings of the 13th International Symposium on Modeling, 2005
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005
Proceedings of the Embedded and Ubiquitous Computing, 2005
Proceedings of the 2005 Design, 2005
Proceedings of the 42nd Design Automation Conference, 2005
Proceedings of the 42nd Design Automation Conference, 2005
Proceedings of the 42nd Design Automation Conference, 2005
Enhancing security through hardware-assisted run-time validation of program data properties.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005
Eliminating memory bottlenecks for a JPEG encoder through distributed logic-memory architecture and computation-unit integrated memory.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
2004
Input space adaptive design: a high-level methodology for optimizing energy and performance.
IEEE Trans. Very Large Scale Integr. Syst., 2004
DESP: A Distributed Economics-Based Subcontracting Protocol for Computation Distribution in Power-Aware Mobile Ad Hoc Networks.
IEEE Trans. Mob. Comput., 2004
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
COWLS: hardware-software cosynthesis of wireless low-power distributed embedded client-server systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004
Profiling Driven Computation Reuse: An Embedded Software Synthesis Technique for Energy and Performance Optimization.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004
Proceedings of the 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 2004
An Energy-Aware Framework for Coordinated Dynamic Software Management in Mobile Computers.
Proceedings of the 12th International Workshop on Modeling, 2004
An Automatic Test Pattern Generation Framework for Combinational Threshold Logic Networks.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004
Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies.
Proceedings of the 2004 Design, 2004
Proceedings of the 2004 Design, 2004
Language Selection for Mobile Systems: Java, C, or Both?
Proceedings of the International Conference on Embedded Systems and Applications, 2004
Evaluating Conditional Statements in Embedded System Software: Systematic Methodologies for Reducing Energy Consumption.
Proceedings of the International Conference on Embedded Systems and Applications, 2004
An Energy-Aware Synthesis Methodology for OS-Driven Multi-Process Embedded Software.
Proceedings of the International Conference on Embedded Systems and Applications, 2004
2003
High-level macro-modeling and estimation techniques for switching activity and power consumption.
IEEE Trans. Very Large Scale Integr. Syst., 2003
A simulation framework for energy-consumption analysis of OS-driven embedded applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003
Power-profile Driven Variable Voltage Sealing for Heterogeneous Distributed Real-time Embedded Systems.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003
PowerHerd: dynamic satisfaction of peak power constraints in interconnection networks.
Proceedings of the 17th Annual International Conference on Supercomputing, 2003
Test Generation for Non-separable RTL Controller-datapath Circuits using a Satisfiability based Approach.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003
Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Heterogeneous Distributed Real-time Embedded Systems.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003
Synthesis of Heterogeneous Distributed Architectures for Memory-Intensive Applications.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003
Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks.
Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), 2003
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003
Software Architectural Transformations: A New Approach to Low Energy Embedded Software.
Proceedings of the 2003 Design, 2003
Proceedings of the International Conference on Compilers, 2003
Proceedings of the Embedded Software for SoC, 2003
2002
IEEE Trans. Very Large Scale Integr. Syst., 2002
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002
IEEE Comput. Archit. Lett., 2002
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002
Hardware-Software Co-Synthesis of Low Power Real-Time Distributed Embedded Systems with Dynamically Reconfigurable FPGAs.
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002
Static and Dynamic Variable Voltage Scheduling Algorithms for Real-Time Heterogeneous Distributed Embedded Systems.
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002
An Economics-based Power-aware Protocol for Computation Distribution in Mobile Ad-Hoc Networks.
Proceedings of the International Conference on Parallel and Distributed Computing Systems, 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Register Binding Based Power Management for High-level Synthesis of Control-Flow Intensive Behaviors.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002
Proceedings of the High Performance Computing, 2002
2001
TAO: regular expression-based register-transfer level testability analysis and optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001
Input Space Adaptive Design: A High-level Methodology for Energy and Performance Optimization.
Proceedings of the 38th Design Automation Conference, 2001
Proceedings of the 38th Design Automation Conference, 2001
Proceedings of the 38th Design Automation Conference, 2001
2000
TAO-BIST: A framework for testability analysis and optimization forbuilt-in self-test of RTL circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000
Incorporating speculative execution into scheduling ofcontrol-flow-intensive designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000
Behavioral Synthesis of Fault Secure Controller/Datapaths Based on Aliasing Probability Analysis.
IEEE Trans. Computers, 2000
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000
COWLS: Hardware-Software Co-Synthesis of Distributed Wireless Low-Power Embedded Client-Server Systems.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000
Power-Conscious Joint Scheduling of Periodic Task Graphs and Aperiodic Tasks in Distributed Real-Time Embedded Systems.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000
Proceedings of the 37th Conference on Design Automation, 2000
1999
IEEE Trans. Very Large Scale Integr. Syst., 1999
IEEE Trans. Very Large Scale Integr. Syst., 1999
IEEE Trans. Parallel Distributed Syst., 1999
Register transfer level power optimization with emphasis on glitch analysis and reduction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999
FACT: a framework for applying throughput and power optimizing transformations to control-flow-intensive behavioral descriptions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999
High-level synthesis of power-optimized and area-optimized circuits from hierarchical data-flow intensive behaviors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999
A low overhead design for testability and test generation technique for core-based systems-on-a-chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999
Corrections to "mogac: a multiobjective genetic algorithm for hardware-software cosynthesis of distributed embedded systems".
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999
IEEE Trans. Computers, 1999
TAO-BIST: A Framework for Testability Analysis and Optimizationb of RTL Circuits for BIST.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999
Proceedings of the 1999 Design, 1999
Common-Case Computation: A High-Level Technique for Power and Performance Optimization.
Proceedings of the 36th Conference on Design Automation, 1999
1998
Integration of hierarchical test generation with behavioral synthesis of controller and data path circuits.
IEEE Trans. Very Large Scale Integr. Syst., 1998
A design-for-testability technique for register-transfer level circuits using control/data flow extraction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998
MOGAC: a multiobjective genetic algorithm for hardware-software cosynthesis of distributed embedded systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998
COHRA: hardware-software cosynthesis of hierarchical heterogeneous distributed embedded systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998
COHRA: Hardware-Software Co-Synthesis of Hierarchical Distributed Embedded System Architectures.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998
Removal of memory access bottlenecks for scheduling control-flow intensive behavioral descriptions.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998
CORDS: hardware-software co-synthesis of reconfigurable real-time distributed embedded systems.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998
Proceedings of the 1998 Design, 1998
CASPER: Concurrent Hardware-Software Co-Synthesis of Hard Real-Time Aperiodic and Periodic Specifications of Embedded System Architectures.
Proceedings of the 1998 Design, 1998
Incorporating Speculative Execution into Scheduling of Control-Flow Intensive Behavioral Descriptions.
Proceedings of the 35th Conference on Design Automation, 1998
Synthesis of Power-Optimized and Area-Optimized Circuits from Hierarchical Behavioral Descriptions.
Proceedings of the 35th Conference on Design Automation, 1998
<i>FACT</i>: A Framework for the Application of Throughput and Power Optimizing Transformations to Control-Flow Intensive Behavioral Descriptions.
Proceedings of the 35th Conference on Design Automation, 1998
Proceedings of the 35th Conference on Design Automation, 1998
Proceedings of the 35th Conference on Design Automation, 1998
1997
IEEE Trans. Parallel Distributed Syst., 1997
Analysis and Randomized Design of Algorithm-Based Fault Tolerant Multiprocessor Systems Under an Extended Model.
IEEE Trans. Parallel Distributed Syst., 1997
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997
Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997
Design for hierarchical testability of RTL circuits obtained by behavioral synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997
A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997
Wavesched: a novel scheduling technique for control-flow intensive behavioral descriptions.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997
MOGAC: a multiobjective genetic algorithm for the co-synthesis of hardware-software embedded systems.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997
COFTA: Hardware-Software Co-Synthesis of Heterogeneous Distributed Embedded System Architectures for Low Overhead Fault Tolerance.
Proceedings of the Digest of Papers: FTCS-27, 1997
Proceedings of the 34st Conference on Design Automation, 1997
Proceedings of the 34st Conference on Design Automation, 1997
Proceedings of the 34st Conference on Design Automation, 1997
1996
Synthesis for parallel scan: applications to partial scan and robust path-delay fault testability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996
Controller re-specification to minimize switching activity in controller/data path circuits.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996
Register-transfer level estimation techniques for switching activity and power consumption.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996
A design for testability technique for RTL circuits using control/data flow extraction.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996
Behavioral Synthesis of Fault Secure Controller?Datapaths using Aliasing Probability Analysis.
Proceedings of the Digest of Papers: FTCS-26, 1996
Proceedings of the 33st Conference on Design Automation, 1996
1995
An ILP Formulation for Low Power Based on Minimizing Switched Capacitance During Data Path Allocation.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
Task Allocation for Safety and Reliability in Distributed Systems.
Proceedings of the 1995 International Conference on Parallel Processing, 1995
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995
Hardware-software co-synthesis of fault-tolerant real-time distributed embedded systems.
Proceedings of the Proceedings EURO-DAC'95, 1995
1994
Design of Algorithm-Based Fault-Tolerant Multiprocessor Systems for Concurrent Error Detection and Fault Diagnosis.
IEEE Trans. Parallel Distributed Syst., 1994
Partitioned Encoding Schemes for Algorithm-Based Fault Tolerance in Massively Parallel Systems.
IEEE Trans. Parallel Distributed Syst., 1994
IEEE Trans. Computers, 1994
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994
Behavioral Synthesis for Hierarchical Testability of Controller/Data Path Circuits with Conditional Branches.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994
1993
IEEE Trans. Parallel Distributed Syst., 1993
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993
IEEE Trans. Computers, 1993
Optimal Design of Checks for Error Detection and Location in Fault-Tolerant Multiprocessor Systems.
IEEE Trans. Computers, 1993
Fault Detection in CVS Parity Trees with Application to Strongly Self-Checking Parity and Two-Rail Checkers.
IEEE Trans. Computers, 1993
Proceedings of the Sixth International Conference on VLSI Design, 1993
A Conditional Resource-Sharing Method for Behavior Synthesis of Highly- Testable Data Paths.
Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993
Proceedings of the 1993 International Conference on Parallel Processing, 1993
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993
Synthesis of Sequential Circuits for Easy Testability Through Performance-Oriented Parallel Partial Scan.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993
Behavioral Synthesis of Highly Testable Data Paths under the Non-Scan and Partial Scan Environments.
Proceedings of the 30th Design Automation Conference. Dallas, 1993
1992
Design and Analysis of Fault-Detecting and Fault-Locating Schedules for Computation DAGs.
Proceedings of the 6th International Parallel Processing Symposium, 1992
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992
Synthesis of Multi-Level Combinational Circuits for Complete Robust Path Delay Fault Testability.
Proceedings of the Digest of Papers: FTCS-22, 1992
1991
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991
Optimal Design of Checks for Error Detection and Location in Fault Tolerant Multiprocessors Systems.
Proceedings of the Fault-Tolerant Computing Systems, Tests, Diagnosis, 1991
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991
Proceedings of the 1991 International Symposium on Fault-Tolerant Computing, 1991
Proceedings of the conference on European design automation, 1991
1990
Strong fault-secure and strongly self-checking domino-CMOS implementations of totally self-checking circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990
Design of robustly testable static CMOS parity trees derived from binary decision diagrams.
Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990
A dependence graph-based approach to the design of algorithm-based fault tolerant systems.
Proceedings of the 20th International Symposium on Fault-Tolerant Computing, 1990
Detection of multiple input bridging and stuck-on faults in CMOS logic circuits using current monitoring.
Proceedings of the European Design Automation Conference, 1990
1989
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989
Design of sufficiently strongly self-checking embedded checkers for systematic and separable codes.
Proceedings of the Computer Design: VLSI in Computers and Processors, 1989
Fault detection in CVS parity trees: application in SSC CVS parity and two-rail checkers.
Proceedings of the Nineteenth International Symposium on Fault-Tolerant Computing, 1989
1988
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988
IEEE Trans. Computers, 1988
Proceedings of the Computer Design: VLSI in Computers and Processors, 1988
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988
1986
Detecting Multiple Faults in CMOS Circuits.
Proceedings of the Proceedings International Test Conference 1986, 1986
1985
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1985