Rajiv V. Joshi

According to our database1, Rajiv V. Joshi authored at least 96 papers between 1997 and 2020.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 2002, "For contributions to chip metallurgy materials and processes, and high performance processor and circuit design.".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
Accurate Inference with Inaccurate RRAM Devices: Statistical Data, Model Transfer, and On-line Adaptation.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Big vs little core for energy-efficient Hadoop computing.
J. Parallel Distributed Comput., 2019

Research From the IEEE IBM AI Compute and Emerging Technology Symposia.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019

Hierarchical Memory System With STT-MRAM and SRAM to Support Transfer and Real-Time Reinforcement Learning in Autonomous Drones.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019

Low Power Design From Moore to AI for nm Era : Invited Paper.
Proceedings of the 26th International Conference on Mixed Design of Integrated Circuits and Systems, 2019

Data Imbalance Handling Approaches for Accurate Statistical Modeling and Yield Analysis of Memory Designs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Resilient Low Voltage Accelerators for High Energy Efficiency.
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019

2018
Sparse Regression Driven Mixture Importance Sampling for Memory Design.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Cascaded and resonant SRAM supply boosting for ultra-low voltage cognitive IoT applications.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

2017
Editorial.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Editorial.
IEEE Trans. Very Large Scale Integr. Syst., 2017

A Low Voltage SRAM Using Resonant Supply Boosting.
IEEE J. Solid State Circuits, 2017

Distributed In-Memory Computing on Binary RRAM Crossbar.
ACM J. Emerg. Technol. Comput. Syst., 2017

Regularized logistic regression for fast importance sampling based SRAM yield analysis.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Yield and energy tradeoffs of an NVLatch design using radial sampling.
Proceedings of the 2017 IEEE International Conference on IC Design and Technology, 2017


Session 5 - Memory for emerging applications.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

Programmable supply boosting techniques for near threshold and wide operating voltage SRAM.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016
A Universal Hardware-Driven PVT and Layout-Aware Predictive Failure Analytics for SRAM.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Guest Editorial Emerging Memories - Technology, Architecture and Applications (Second Issue).
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

Guest Editorial Emerging Memories - Technology, Architecture and Applications (First Issue).
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

Overview of Circuits, Systems, and Applications of Spintronics.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

Efficient analog circuit optimization using sparse regression and error margining.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Characterizing Hadoop applications on microservers for performance and energy efficiency optimizations.
Proceedings of the 2016 IEEE International Symposium on Performance Analysis of Systems and Software, 2016

Big biomedical image processing hardware acceleration: A case study for K-means and image filtering.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Corrections to "Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction".
IEEE Trans. Very Large Scale Integr. Syst., 2015

14nm FinFET based supply voltage boosting techniques for extreme low Vmin operation.
Proceedings of the Symposium on VLSI Circuits, 2015

2014
The resilience wall: Cross-layer solution strategies.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

Impact of FinFET technology for power gating in nano-scale design.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Statistical methodology for modeling non-IID memory fails events.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Robust bias temperature instability refresh design and methodology for memory cell recovery.
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014

A New Field-assisted Access Scheme of STT-RAM with Self-reference Capability.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Design technology co-optimization for 10 nm and beyond.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

TCAD structure synthesis and capacitance extraction of a voltage-controlled oscillator using automated layout-to-device synthesis methodology.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013
3-D-TCAD-Based Parasitic Capacitance Extraction for Emerging Multigate Devices and Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Efficient Methodologies for 3-D TCAD Modeling of Emerging Devices and Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Hardware-corroborated Variability-Aware SRAM Methodology.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

Welcome to ISQED 2013.
Proceedings of the International Symposium on Quality Electronic Design, 2013

2012
Isolated Preset Architecture for a 32nm SOI embedded DRAM macro.
Proceedings of the Symposium on VLSI Circuits, 2012

A novel sample reuse methodology for fast statistical simulations with applications to manufacturing variability.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

A thermal and process variation aware MTJ switching model and its applications in soft error analysis.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Yield estimation via multi-cones.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
The Impact of Statistical Leakage Models on Design Yield Estimation.
VLSI Design, 2011

A Novel Column-Decoupled 8T Cell for Low-Power Differential and Domino-Based SRAM Design.
IEEE Trans. Very Large Scale Integr. Syst., 2011

A Tutorial on Enhancing the Level-of-Learning through ICT-Enabled Teaching in Engineering Education.
Proceedings of the 2011 IEEE International Conference on Technology for Education, 2011

Accelerated statistical simulation via on-demand Hermite spline interpolations.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Universal statistical cure for predicting memory loss.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

2010
The Dawn of Predictive Chip Yield Design: Along and Beyond the Memory Lane.
IEEE Des. Test Comput., 2010

FinFET SRAM Design.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

Use of scalable Parametric Measurement Macro to improve semiconductor technology characterization and product test.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Statistical leakage modeling for accurate yield analysis: the CDF matching method and its alternatives.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

2009
Design of Sub-90 nm Low-Power and Variation Tolerant PD/SOI SRAM Cell Based on Dynamic Stability Metrics.
IEEE J. Solid State Circuits, 2009

The impact of BEOL lithography effects on the SRAM cell performance and yield.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Statistical yield analysis of silicon-on-insulator embedded DRAM.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

An elegant hardware-corroborated statistical repair and test methodology for conquering aging effects.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

2008
Variability Analysis for sub-100nm PD/SOI Sense-Amplifier.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

A Root-Finding Method for Assessing SRAM Stability.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Statistical Evaluation of Split Gate Opportunities for Improved 8T/6T Column-Decoupled SRAM Cell Yield.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

SRAM methodology for yield and power efficiency: per-element selectable supplies and memory reconfiguration schemes.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

2007
Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50nm double gate devices.
Microelectron. J., 2007

A High-Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate Biasing Scheme in FinFET Technology.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Gate Leakage Effects on Yield and Design Considerations of PD/SOI SRAM Designs.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

A floating-body dynamic supply boosting technique for low-voltage sram in nanoscale PD/SOI CMOS technologies.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

A Disturb Decoupled Column Select 8T SRAM Cell.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
Technology Impacts on Sub-90nm CMOS Circuit Design and Design Methodologies.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

A 5.6GHz 64kB Dual-Read Data Cache for the POWER6TM Processor.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

Tutorial 1: Emerging Technologies for VLSI Design.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events.
Proceedings of the 43rd Design Automation Conference, 2006

A novel variation-aware low-power keeper architecture for wide fan-in dynamic gates.
Proceedings of the 43rd Design Automation Conference, 2006

2005
Direct Temperature Measurement for VLSI Circuits and 3-D Modeling of Self-Heating in Sub-0.13 mum SOI Technologies.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Design of sub-90nm Circuits and Design Methodologies.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

A Low-Overhead Virtual Rail Technique for SRAM Leakage Power Reduction.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

2004
A Novel Technique For Steady State Analysis For VLSI Circuits In Partially Depleted SOI.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Nanoscale CMOS circuit leakage power reduction by double-gate device.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

2003
PD/SOI SRAM performance in presence of gate-to-body tunneling current.
IEEE Trans. Very Large Scale Integr. Syst., 2003

Influence and model of gate oxide breakdown on CMOS inverters.
Microelectron. Reliab., 2003

Preface.
IBM J. Res. Dev., 2003

Design of Deep Sub-Micron CMOS Circuits.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Design Considerations of Scaled Sub-0.1 ?m PD/SOI CMOS Circuits.
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

Strained-si devices and circuits for low-power applications.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

New optimal design strategies and analysis of ultra-low leakage circuits for nano-scale SOI technology.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Design and CAD Challenges in sub-90nm CMOS Technologies.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

2002
Analysis of the effect of the gate oxide breakdown on SRAM stability.
Microelectron. Reliab., 2002

2001
IBM's Blue Logic Design Methodology-Circuits and Physical Design.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Design Of Provably Correct Storage Arrays.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuit styles and strategies for low power VLSI design.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

SOI for asynchronous dynamic circuits.
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001

2000
A Low Power 900 MHz Register File (8 Ports, 32 Words x 64 Bits) in 1.8V, 0.25µm SOI Technology.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

"Cool low power" 1GHz multi-port register file and dynamic latch in 1.8 V, 0.25 mum SOI and bulk technology (poster session).
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

1999
Design Considerations and Implementation of a High Performance Dynamic Register File.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

1998

1997
Development of a High Bandwidth Merged Logic/DRAM Multimedia Chip.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

A Pulse-To-Static Conversion Latch with a Self-Timed Control Circuit.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997


  Loading...