Rajiv V. Joshi
Orcid: 0009-0007-7486-1531
According to our database1,
Rajiv V. Joshi
authored at least 138 papers
between 1997 and 2024.
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Bibliography
2024
Paving the Way for Pass Disturb Free Vertical NAND Storage via A Dedicated and String-Compatible Pass Gate.
CoRR, 2024
Reliable and Energy-Efficient Diabetic Retinopathy Screening Using Memristor-Based Neural Networks.
IEEE Access, 2024
2023
A Best Balance Ratio Ordered Feature Selection Methodology for Robust and Fast Statistical Analysis of Memory Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2023
IEEE Trans. Emerg. Top. Comput. Intell., February, 2023
IEEE Trans. Biomed. Circuits Syst., February, 2023
Powering Disturb-Free Reconfigurable Computing and Tunable Analog Electronics with Dual-Port Ferroelectric FET.
CoRR, 2023
An Energy-Efficient Multi-bit Current-based Analog Compute-In-Memory Architecture and design Methodology.
Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023
(Invited) Predictive analytics for cryogenic CMOS in future quantum computing systems.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
Read-disturb Detection Methodology for RRAM-based Computation-in-Memory Architecture.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
A 115.1 TOPS/W, 12.1 TOPS/mm<sup>2</sup> Computation-in-Memory using Ring-Oscillator based ADC for Edge AI.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
A Fully Differential 4-Bit Analog Compute-In-Memory Architecture for Inference Application.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
2022
Delay Modulation in Separately Driven Delay Cells Utilized for the Generation of High-Performance Multiphase Signals Using ROs.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Group LARS-Based Iterative Reweighted Least Squares Methodology for Efficient Statistical Modeling of Memory Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Exploring Model Stability of Deep Neural Networks for Reliable RRAM-Based In-Memory Acceleration.
IEEE Trans. Computers, 2022
A Cryo-CMOS Low-Power Semi-Autonomous Transmon Qubit State Controller in 14-nm FinFET Technology.
IEEE J. Solid State Circuits, 2022
A Voltage-Controlled, Oscillation-Based ADC Design for Computation-in-Memory Architectures Using Emerging ReRAMs.
ACM J. Emerg. Technol. Comput. Syst., 2022
Ferroelectric FET based Context-Switching FPGA Enabling Dynamic Reconfiguration for Adaptive Deep Learning Machines.
CoRR, 2022
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Asymmetric Double-Gate Ferroelectric FET to Decouple the Tradeoff Between Thickness Scaling and Memory Window.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Proceedings of the IEEE International Test Conference, 2022
A Cryo-CMOS Low-Power Semi-Autonomous Qubit State Controller in 14nm FinFET Technology.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
A 65nm Compute-In-Memory 7T SRAM Macro Supporting 4-bit Multiply and Accumulate Operation by Employing Charge Sharing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
CIM-based Robust Logic Accelerator using 28 nm STT-MRAM Characterization Chip Tape-out.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
SRIF: Scalable and Reliable Integrate and Fire Circuit ADC for Memristor-Based CIM Architectures.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
24.1 A 6.2 GHz Single Ended Current Sense Amplifier (CSA) Based Compileable 8T SRAM in 7nm FinFET Technology.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the IEEE International Reliability Physics Symposium, 2021
Unbalanced Bit-slicing Scheme for Accurate Memristor-based Neural Network Architecture.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021
2020
Accurate Inference with Inaccurate RRAM Devices: Statistical Data, Model Transfer, and On-line Adaptation.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
J. Parallel Distributed Comput., 2019
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019
Hierarchical Memory System With STT-MRAM and SRAM to Support Transfer and Real-Time Reinforcement Learning in Autonomous Drones.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019
Proceedings of the 26th International Conference on Mixed Design of Integrated Circuits and Systems, 2019
Data Imbalance Handling Approaches for Accurate Statistical Modeling and Yield Analysis of Memory Designs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019
2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
Cascaded and resonant SRAM supply boosting for ultra-low voltage cognitive IoT applications.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018
2017
IEEE J. Solid State Circuits, 2017
ACM J. Emerg. Technol. Comput. Syst., 2017
Regularized logistic regression for fast importance sampling based SRAM yield analysis.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017
Proceedings of the 2017 IEEE International Conference on IC Design and Technology, 2017
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
Programmable supply boosting techniques for near threshold and wide operating voltage SRAM.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
2016
A Universal Hardware-Driven PVT and Layout-Aware Predictive Failure Analytics for SRAM.
IEEE Trans. Very Large Scale Integr. Syst., 2016
Guest Editorial Emerging Memories - Technology, Architecture and Applications (Second Issue).
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016
Guest Editorial Emerging Memories - Technology, Architecture and Applications (First Issue).
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016
Characterizing Hadoop applications on microservers for performance and energy efficiency optimizations.
Proceedings of the 2016 IEEE International Symposium on Performance Analysis of Systems and Software, 2016
Big biomedical image processing hardware acceleration: A case study for K-means and image filtering.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
Corrections to "Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction".
IEEE Trans. Very Large Scale Integr. Syst., 2015
Proceedings of the Symposium on VLSI Circuits, 2015
2014
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
Robust bias temperature instability refresh design and methodology for memory cell recovery.
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
TCAD structure synthesis and capacitance extraction of a voltage-controlled oscillator using automated layout-to-device synthesis methodology.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
2013
3-D-TCAD-Based Parasitic Capacitance Extraction for Emerging Multigate Devices and Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2013
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013
Proceedings of the International Symposium on Quality Electronic Design, 2013
2012
Proceedings of the Symposium on VLSI Circuits, 2012
A novel sample reuse methodology for fast statistical simulations with applications to manufacturing variability.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
A thermal and process variation aware MTJ switching model and its applications in soft error analysis.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
2011
VLSI Design, 2011
A Novel Column-Decoupled 8T Cell for Low-Power Differential and Domino-Based SRAM Design.
IEEE Trans. Very Large Scale Integr. Syst., 2011
A Tutorial on Enhancing the Level-of-Learning through ICT-Enabled Teaching in Engineering Education.
Proceedings of the 2011 IEEE International Conference on Technology for Education, 2011
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011
2010
IEEE Des. Test Comput., 2010
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010
Use of scalable Parametric Measurement Macro to improve semiconductor technology characterization and product test.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
Statistical leakage modeling for accurate yield analysis: the CDF matching method and its alternatives.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010
2009
Design of Sub-90 nm Low-Power and Variation Tolerant PD/SOI SRAM Cell Based on Dynamic Stability Metrics.
IEEE J. Solid State Circuits, 2009
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
An elegant hardware-corroborated statistical repair and test methodology for conquering aging effects.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
2008
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
Statistical Evaluation of Split Gate Opportunities for Improved 8T/6T Column-Decoupled SRAM Cell Yield.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
SRAM methodology for yield and power efficiency: per-element selectable supplies and memory reconfiguration schemes.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008
2007
Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50nm double gate devices.
Microelectron. J., 2007
A High-Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate Biasing Scheme in FinFET Technology.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
A floating-body dynamic supply boosting technique for low-voltage sram in nanoscale PD/SOI CMOS technologies.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
2006
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events.
Proceedings of the 43rd Design Automation Conference, 2006
Proceedings of the 43rd Design Automation Conference, 2006
2005
Direct Temperature Measurement for VLSI Circuits and 3-D Modeling of Self-Heating in Sub-0.13 mum SOI Technologies.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005
Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005
A novel circuit topology for generating and validating digitally sense amplifier differentials for bulk and SOI.
Proceedings of the 31st European Solid-State Circuits Conference, 2005
2004
A Novel Technique For Steady State Analysis For VLSI Circuits In Partially Depleted SOI.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004
Proceedings of the 33rd European Solid-State Circuits Conference, 2004
2003
IEEE Trans. Very Large Scale Integr. Syst., 2003
Microelectron. Reliab., 2003
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003
New optimal design strategies and analysis of ultra-low leakage circuits for nano-scale SOI technology.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003
New digital circuit techniques for total standby leakage reduction in nano-scale SOI technology.
Proceedings of the ESSCIRC 2003, 2003
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003
2002
Microelectron. Reliab., 2002
2001
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001
Mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuit styles and strategies for low power VLSI design.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001
2000
IEEE J. Solid State Circuits, 2000
A Low Power 900 MHz Register File (8 Ports, 32 Words x 64 Bits) in 1.8V, 0.25µm SOI Technology.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000
"Cool low power" 1GHz multi-port register file and dynamic latch in 1.8 V, 0.25 mum SOI and bulk technology (poster session).
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000
1999
IEEE J. Solid State Circuits, 1999
Design Considerations and Implementation of a High Performance Dynamic Register File.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999
1998
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998
1997
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997