Ajay N. Bhoj

According to our database, Ajay N. Bhoj authored at least 12 papers between 2009 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2016

Fast FinFET Device Simulation under Process-Voltage Variations Using an Assisted Speed-Up Mechanism.

Sourindra Chaudhuri, Ajay N. Bhoj, Debajit Bhattacharya, Niraj K. Jha

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

2015

Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction.

Rajiv V. Joshi, Keunwoo Kim, Rouwaida Kanj, Ajay N. Bhoj, Matthew M. Ziegler, Phil Oldiges, Pranita Kerber, Robert Wong, Terence Hook, Sudesh Saroop, Carl Radens, Chun-Chen Yeh

IEEE Trans. Very Large Scale Integr. Syst., 2015

Design of Efficient Content Addressable Memories in High-Performance FinFET Technology.

Debajit Bhattacharya, Ajay N. Bhoj, Niraj K. Jha

IEEE Trans. Very Large Scale Integr. Syst., 2015

2014

Parasitics-Aware Design of Symmetric and Asymmetric Gate-Workfunction FinFET SRAMs.

Ajay N. Bhoj, Niraj K. Jha

IEEE Trans. Very Large Scale Integr. Syst., 2014

2013

3-D-TCAD-Based Parasitic Capacitance Extraction for Emerging Multigate Devices and Circuits.

Ajay N. Bhoj, Rajiv V. Joshi, Niraj K. Jha

IEEE Trans. Very Large Scale Integr. Syst., 2013

Design of Logic Gates and Flip-Flops in High-Performance FinFET Technology.

Ajay N. Bhoj, Niraj K. Jha

IEEE Trans. Very Large Scale Integr. Syst., 2013

Efficient Methodologies for 3-D TCAD Modeling of Emerging Devices and Circuits.

Ajay N. Bhoj, Rajiv V. Joshi, Niraj K. Jha

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

2011

Design of ultra-low-leakage logic gates and flip-flops in high-performance FinFET technology.

Ajay N. Bhoj, Niraj K. Jha

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

2010

Gated-diode FinFET DRAMs: Device and circuit design-considerations.

Ajay N. Bhoj, Niraj K. Jha

ACM J. Emerg. Technol. Comput. Syst., 2010

Fault modeling for FinFET circuits.

Muzaffer O. Simsir, Ajay N. Bhoj, Niraj K. Jha

Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, 2010

Die-level leakage power analysis of FinFET circuits considering process variations.

Prateek Mishra, Ajay N. Bhoj, Niraj K. Jha

Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

2009

Pragmatic design of gated-diode FinFET DRAMs.

Ajay N. Bhoj, Niraj K. Jha

Proceedings of the 27th International Conference on Computer Design, 2009