Deepak Chauhan

According to our database, Deepak Chauhan authored at least 4 papers between 2012 and 2017.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2017

Managing Trace Summaries to Minimize Stalls During Postsilicon Validation.

Sandeep Chandran, Preeti Ranjan Panda, Smruti R. Sarangi, Ayan Bhattacharyya, Deepak Chauhan, Sharad Kumar

IEEE Trans. Very Large Scale Integr. Syst., 2017

2016

Extending trace history through tapered summaries in post-silicon validation.

Sandeep Chandran, Preeti Ranjan Panda, Deepak Chauhan, Sharad Kumar, Smruti R. Sarangi

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2014

UVM based STBUS verification IP for verifying SoC architectures.

Pranay Samanta, Deepak Chauhan, Sujay Deb, Piyush Kumar Gupta

Proceedings of the 18th International Symposium on VLSI Design and Test, 2014

2012

Post Silicon Validation of Digital Radio Interfaces.

Deepak Chauhan, Sharad Kumar, Manoj Sharma

Proceedings of the International Symposium on Electronic System Design, 2012