Sandeep Chandran

Orcid: 0000-0001-7110-5668

According to our database1, Sandeep Chandran authored at least 11 papers between 2002 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Dynamic Ineffectuality-based Clustered Architectures.
CoRR, 2023

SANNA: Secure Acceleration of Neural Network Applications.
Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023

2019
DHOOM: Reusing Design-for-Debug Hardware for Online Monitoring.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2017
Managing Trace Summaries to Minimize Stalls During Postsilicon Validation.
IEEE Trans. Very Large Scale Integr. Syst., 2017

2016
Area-Aware Cache Update Trackers for Postsilicon Validation.
IEEE Trans. Very Large Scale Integr. Syst., 2016

A Generic Implementation of Barriers Using Optical Interconnects.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Extending trace history through tapered summaries in post-silicon validation.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Fundamental Results for a Generic Implementation of Barriers using Optical Interconnects.
CoRR, 2015

2014
Architectural Support for Handling Jitterin Shared Memory Based Parallel Applications.
IEEE Trans. Parallel Distributed Syst., 2014

2013
Space sensitive cache dumping for post-silicon validation.
Proceedings of the Design, Automation and Test in Europe, 2013

2002
Heuristic random optimizer-version II.
Proceedings of the American Control Conference, 2002


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