Smruti R. Sarangi

Orcid: 0000-0002-1657-8523

According to our database1, Smruti R. Sarangi authored at least 127 papers between 2003 and 2023.

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Bibliography

2023
VarSim: A fast process variation-aware thermal modeling methodology using Green's functions.
Microelectron. J., December, 2023

Toward an Optimal Countermeasure for Cache Side-Channel Attacks.
IEEE Embed. Syst. Lett., September, 2023

Managing Large Enclaves in a Data Center.
CoRR, 2023

SparseLock: Securing Neural Network Models in Deep Learning Accelerators.
CoRR, 2023

ExWarp: Extrapolation and Warping-based Temporal Supersampling for High-frequency Displays.
CoRR, 2023

Efficiently Using Polar Codes in 5G Base Stations to Enhance Rural Connectivity.
CoRR, 2023

SecOComp: A Fast and Secure Simultaneous Compression and Encryption Scheme.
CoRR, 2023

FaaSched: A Jitter-Aware Serverless Scheduler.
CoRR, 2023

JASS: A Flexible Checkpointing System for NVM-based Systems.
CoRR, 2023

Minimizing the Motion-to-Photon-delay (MPD) in Virtual Reality Systems.
CoRR, 2023

SnapStore: A Snapshot Storage System for Serverless Systems.
Proceedings of the 24th International Middleware Conference, 2023

SmrtComp: Intelligent and Online CAN Data Compression.
Proceedings of the 25th IEEE International Conference on Intelligent Transportation Systems, 2023

Securator: A Fast and Secure Neural Processing Unit.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

JASS: A Tunable Checkpointing System for NVM-Based Systems.
Proceedings of the 30th IEEE International Conference on High Performance Computing, 2023

Perspector: Benchmarking Benchmark Suites.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022
Game Theory-Based Parameter Tuning for Energy-Efficient Path Planning on Modern UAVs.
ACM Trans. Cyber Phys. Syst., 2022

Performance and Power Prediction for Concurrent Execution on GPUs.
ACM Trans. Archit. Code Optim., 2022

A survey and experimental analysis of checkpointing techniques for energy harvesting devices.
J. Syst. Archit., 2022

Hardware-assisted mechanisms to enforce control flow integrity: A comprehensive survey.
J. Syst. Archit., 2022

A Novel Meta-predictor based Algorithm for Testing VLSI Circuits.
CoRR, 2022

A Comprehensive Benchmark Suite for Intel SGX.
CoRR, 2022

Seculator: A Fast and Secure Neural Processing Unit.
CoRR, 2022

PredStereo: An Accurate Real-time Stereo Vision System.
Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision, 2022

NanoLeak: A Fast Analytical Green's Function-based Leakage-aware Thermal Simulator.
Proceedings of the 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, 2022

SecureLease: Maintaining Execution Control in The Wild using Intel SGX.
Proceedings of the Middleware '22: 23rd International Middleware Conference, Quebec, QC, Canada, November 7, 2022

CmpctArch: A Generic Low Power Architecture for Compact Data Structures in Energy Harvesting Devices.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

HAJPAQUE: Hardware Accelerator for JSON Parsing, Querying and Schema Validation.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

SGXGauge: A Comprehensive Benchmark Suite for Intel SGX.
Proceedings of the International IEEE Symposium on Performance Analysis of Systems and Software, 2022

Poster Abstract: Polar Code-based Approximate Communication System for Multimedia Web Pages.
Proceedings of the 21st ACM/IEEE International Conference on Information Processing in Sensor Networks, 2022

Perspectives on Teaching Computer Architecture in Developing Countries.
Proceedings of the COMPUTE 2022, Jaipur, India, November 9-11, 2022, 2022

2021
A Formal Approach to Accountability in Heterogeneous Systems-on-Chip.
IEEE Trans. Dependable Secur. Comput., 2021

A survey of hardware architectures for generative adversarial networks.
J. Syst. Archit., 2021

Accelerating CNN Inference on ASICs: A Survey.
J. Syst. Archit., 2021

Page Table Management for Heterogeneous Memory Systems.
CoRR, 2021

Variability-Aware Thermal Simulation using CNNs.
Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021

ISAMod: A Tool for Designing ASIPs by Comparing Different ISAs.
Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021

Game Theory-Based Parameter-Tuning for Path Planning of UAVs.
Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021

A Fast Compact Thermal Model For Smart Phones.
Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021

SecureFS: A Secure File System for Intel SGX.
Proceedings of the RAID '21: 24th International Symposium on Research in Attacks, 2021

Radiant: efficient page table management for tiered memory systems.
Proceedings of the ISMM '21: 2021 ACM SIGPLAN International Symposium on Memory Management, 2021

EHDSktch: A Generic Low Power Architecture for Sketching in Energy Harvesting Devices.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020
A Fast Leakage-Aware Green's-Function-Based Thermal Simulator for 3-D Chips.
IEEE Trans. Very Large Scale Integr. Syst., 2020

ChunkedTejas: A Chunking-based Approach to Parallelizing a Trace-Driven Architectural Simulator.
ACM Trans. Model. Comput. Simul., 2020

VisSched: An Auction-Based Scheduler for Vision Workloads on Heterogeneous Processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Enhancing Network-on-Chip Performance by Reusing Trace Buffers.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

GPUOPT: Power-efficient Photonic Network-on-Chip for a Scalable GPU.
ACM J. Emerg. Technol. Comput. Syst., 2020

Predict, Share, and Recycle Your Way to Low-power Nanophotonic Networks.
ACM J. Emerg. Technol. Comput. Syst., 2020

SecONet: A Security Framework for a Photonic Network-on-Chip.
Proceedings of the 14th IEEE/ACM International Symposium on Networks-on-Chip, 2020

SoftMon: A Tool to Compare Similar Open-source Software from a Performance Perspective.
Proceedings of the MSR '20: 17th International Conference on Mining Software Repositories, 2020

Performance Prediction for Multi-Application Concurrency on GPUs.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2020

VarSim: A Fast and Accurate Variability and Leakage Aware Thermal Simulator.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
Radio Propagation Characteristics-based Spoofing Attack Prevention on Wireless Connected Devices.
J. Inf. Process., 2019

BigBus: A Scalable Optical Interconnect.
ACM J. Emerg. Technol. Comput. Syst., 2019

A Survey of Chip-level Thermal Simulators.
ACM Comput. Surv., 2019

A Survey of On-Chip Optical Interconnects.
ACM Comput. Surv., 2019

A Reference Architecture for Smart and Software-defined Buildings.
CoRR, 2019

A Reference Architecture for Smart and Software-Defined Buildings.
Proceedings of the IEEE International Conference on Smart Computing, 2019

Power efficient photonic network-on-chip for a scalable GPU.
Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip, 2019

NanoTherm: An Analytical Fourier-Boltzmann Framework for Full Chip Thermal Simulations.
Proceedings of the International Conference on Computer-Aided Design, 2019

FlexiCheck: An Adaptive Checkpointing Architecture for Energy Harvesting Devices.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

F-LaaS: A Control-Flow-Attack Immune License-as-a-Service Model.
Proceedings of the 2019 IEEE International Conference on Services Computing, 2019

2018
Reusing Trace Buffers as Victim Caches.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Providing Accountability in Heterogeneous Systems-on-Chip.
ACM Trans. Embed. Comput. Syst., 2018

Task Assignment Algorithms for Multicore Platforms with Process Variations.
J. Low Power Electron., 2018

Is Leakage Power a Linear Function of Temperature?
CoRR, 2018

Energy efficient scheduling in IoT networks.
Proceedings of the 33rd Annual ACM Symposium on Applied Computing, 2018

Probabilistic Sequential Consistency in Social Networks.
Proceedings of the 25th IEEE International Conference on High Performance Computing, 2018

HPXA: A highly parallel XML parser.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Managing Trace Summaries to Minimize Stalls During Postsilicon Validation.
IEEE Trans. Very Large Scale Integr. Syst., 2017

ParTejas: A Parallel Simulator for Multicore Processors.
ACM Trans. Model. Comput. Simul., 2017

Optical Overlay NUCA: A High-Speed Substrate for Shared L2 Caches.
ACM J. Emerg. Technol. Comput. Syst., 2017

Internet of Things: Architectures, Protocols, and Applications.
J. Electr. Comput. Eng., 2017

Sensitivity Analysis of Core Specialization Techniques.
CoRR, 2017

Schedtask: a hardware-assisted task scheduler.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

NUPLet: A Photonic Based Multi-Chip NUCA Architecture.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Expander: Lock-Free Cache for a Concurrent Data Structure.
Proceedings of the 24th IEEE International Conference on High Performance Computing, 2017

A fast leakage aware thermal simulator for 3D chips.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

A hardware implementation of the MCAS synchronization primitive.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Reusing trace buffers to enhance cache performance.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

POSTER: BigBus: A Scalable Optical Interconnect.
Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques, 2017

2016
Area-Aware Cache Update Trackers for Postsilicon Validation.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Lock-Free and Wait-Free Slot Scheduling Algorithms.
IEEE Trans. Parallel Distributed Syst., 2016

FluidCheck: A Redundant Threading-Based Approach for Reliable Execution in Manycore Processors.
ACM Trans. Archit. Code Optim., 2016

A Generic Implementation of Barriers Using Optical Interconnects.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

pTask: A smart prefetching scheme for OS intensive applications.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

SecCheck: A Trustworthy System with Untrusted Components.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Leakage Power Aware Task Assignment Algorithms for Multicore Platforms.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Noise Aware Scheduling in Data Centers.
Proceedings of the 2016 International Conference on Supercomputing, 2016

A Wait-Free Stack.
Proceedings of the Distributed Computing and Internet Technology, 2016

Extending trace history through tapered summaries in post-silicon validation.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
FP-NUCA: A Fast NOC Layer for Implementing Large NUCA Caches.
IEEE Trans. Parallel Distributed Syst., 2015

Tejas Simulator : Validation against Hardware.
CoRR, 2015

Fundamental Results for a Generic Implementation of Barriers using Optical Interconnects.
CoRR, 2015

Tejas: A java based versatile micro-architectural simulator.
Proceedings of the 25th International Workshop on Power and Timing Modeling, 2015

SecX: A Framework for Collecting Runtime Statistics for SoCs with Multiple Accelerators.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Optimal Power Efficient Photonic SWMR Buses.
Proceedings of the 2015 Workshop on Exploiting Silicon Photonics for Energy-Efficient High Performance Computing, 2015

ColdBus: A Near-Optimal Power Efficient Optical Bus.
Proceedings of the 22nd IEEE International Conference on High Performance Computing, 2015

2014
Architectural Support for Handling Jitterin Shared Memory Based Parallel Applications.
IEEE Trans. Parallel Distributed Syst., 2014

Processor power estimation techniques: a survey.
Int. J. High Perform. Syst. Archit., 2014

Three Experiments to Analyze the Nature of the Heat Spreader.
CoRR, 2014

ParTejas: A parallel simulator for multicore processors.
Proceedings of the 2014 IEEE International Symposium on Performance Analysis of Systems and Software, 2014

Software Transactional Memory Friendly Slot Schedulers.
Proceedings of the Distributed Computing and Internet Technology, 2014

Optical overlay NUCA: A high speed substrate for shared L2 caches.
Proceedings of the 21st International Conference on High Performance Computing, 2014

GpuTejas: A parallel simulator for GPU architectures.
Proceedings of the 21st International Conference on High Performance Computing, 2014

TriKon: A hypervisor aware manycore processor.
Proceedings of the 21st International Conference on High Performance Computing, 2014

RADIR: Lock-free and wait-free bandwidth allocation models for solid state drives.
Proceedings of the 21st International Conference on High Performance Computing, 2014

LightSim: A leakage aware ultrafast temperature simulator.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Amdahl's law in the era of process variation.
Int. J. High Perform. Syst. Archit., 2013

A survey of checker architectures.
ACM Comput. Surv., 2013

Space sensitive cache dumping for post-silicon validation.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
IT Infrastructure for Providing Energy-as-a-Service to Electric Vehicles.
IEEE Trans. Smart Grid, 2012

Efficient on-line algorithm for maintaining k-cover of sparse bit-strings.
Proceedings of the IARCS Annual Conference on Foundations of Software Technology and Theoretical Computer Science, 2012

2011
Virtual base station pool: towards a wireless network cloud for radio access networks.
Proceedings of the 8th Conference on Computing Frontiers, 2011

2010
DUST: a generalized notion of similarity between uncertain time series.
Proceedings of the 16th ACM SIGKDD International Conference on Knowledge Discovery and Data Mining, 2010

2009
Theoretical Framework for Eliminating Redundancy in Workflows.
Proceedings of the 2009 IEEE International Conference on Services Computing (SCC 2009), 2009

2008
EVAL: Utilizing processors with variation-induced timing errors.
Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), 2008

2007
Techniques to Mitigate the Effects of Congenital Faults in Processors
PhD thesis, 2007

Patching Processor Design Errors with Programmable Hardware.
IEEE Micro, 2007

A Model for Timing Errors in Processors with Parameter Variation.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Threshold Voltage Variation Effects on Aging-Related Hard Failure Rates.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

ReCycle: : pipeline adaptation to tolerate process variation.
Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007

2006
Energy-Efficient Thread-Level Speculation.
IEEE Micro, 2006

Phoenix: Detecting and Recovering from Permanent Processor Design Bugs with Programmable Hardware.
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 2006

CADRE: Cycle-Accurate Deterministic Replay for Hardware Debugging.
Proceedings of the 2006 International Conference on Dependable Systems and Networks (DSN 2006), 2006

2005
ReSlice: Selective Re-Execution of Long-Retired Misspeculated Instructions Using Forward Slicing.
Proceedings of the 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-38 2005), 2005

Thread-Level Speculation on a CMP can be energy efficient.
Proceedings of the 19th Annual International Conference on Supercomputing, 2005

2003
A scalable, efficient and general Monte Carlo scheme for generating synthetic web request streams.
Comput. Syst. Sci. Eng., 2003


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