Deepak Vungarala

Orcid: 0009-0000-8659-2040

According to our database1, Deepak Vungarala authored at least 10 papers between 2023 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2025
LIMCA: LLM for Automating Analog In-Memory Computing Architecture Design Exploration.
CoRR, March, 2025

TPU-Gen: LLM-Driven Custom Tensor Processing Unit Generator.
CoRR, March, 2025

SA-DS: A Dataset for Large Language Model-Driven AI Accelerator Design Generation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

From Prompt to Accelerator: A Perspective on LLM-Based Analog In-Memory Accelerator Design Automation.
Proceedings of the Great Lakes Symposium on VLSI 2025, GLSVLSI 2025, New Orleans, LA, USA, 30 June 2025, 2025

Maximizing Sub-Array Resource Utilization in Digital Processing-in-Memory: A Versatile Hardware-Aware Approach.
Proceedings of the Great Lakes Symposium on VLSI 2025, GLSVLSI 2025, New Orleans, LA, USA, 30 June 2025, 2025

LLM-IMC: Automating Analog In-Memory Computing Architecture Generation with Large Language Models.
Proceedings of the 33rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2025

2024
A Dataset for Large Language Model-Driven AI Accelerator Generation.
CoRR, 2024

SPICEPilot: Navigating SPICE Code Generation and Simulation with AI Guidance.
Proceedings of the IEEE International Conference on Rebooting Computing, 2024

2023
Comparative Study of Low Bit-width DNN Accelerators: Opportunities and Challenges.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

The Pinch Sensor: An Input Device for In-Hand Manipulation with the Index Finger and Thumb.
Proceedings of the IEEE/ASME International Conference on Advanced Intelligent Mechatronics, 2023


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