Dionysios Filippas

Orcid: 0000-0002-4729-3336

According to our database1, Dionysios Filippas authored at least 11 papers between 2022 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Links

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Bibliography

2024
Error Checking for Sparse Systolic Tensor Arrays.
CoRR, 2024

2023
Synthesis of Approximate Parallel-Prefix Adders.
IEEE Trans. Very Large Scale Integr. Syst., November, 2023

Streaming Dilated Convolution Engine.
IEEE Trans. Very Large Scale Integr. Syst., March, 2023

Exploiting data encoding and reordering for low-power streaming in systolic arrays.
Microprocess. Microsystems, 2023

The Case for Asymmetric Systolic Array Floorplanning.
CoRR, 2023

Low-Power Data Streaming in Systolic Arrays with Bus-Invert Coding and Zero-Value Clock Gating.
Proceedings of the 12th International Conference on Modern Circuits and Systems Technologies, 2023

ArrayFlex: A Systolic Array Architecture with Configurable Transparent Pipelining.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Reduced-Precision Floating-Point Arithmetic in Systolic Arrays with Skewed Pipelines.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023

2022
Low-Cost Online Convolution Checksum Checker.
IEEE Trans. Very Large Scale Integr. Syst., 2022

LeapConv: An Energy-Efficient Streaming Convolution Engine with Reconfigurable Stride.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

FusedGCN: A Systolic Three-Matrix Multiplication Architecture for Graph Convolutional Networks.
Proceedings of the 33rd IEEE International Conference on Application-specific Systems, 2022


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