Donald Kline Jr.

Orcid: 0000-0002-4414-1513

Affiliations:
  • University of Pittsburgh, ECE Department, PA, USA


According to our database1, Donald Kline Jr. authored at least 28 papers between 2015 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2021
A CASTLE With TOWERs for Reliable, Secure Phase-Change Memory.
IEEE Trans. Computers, 2021

Tuning Memory Fault Tolerance on the Edge.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

2020
Sustainable disturbance crosstalk mitigation in deeply scaled phase-change memory.
Sustain. Comput. Informatics Syst., 2020

FLOWER and FaME: A Low Overhead Bit-Level Fault-map and Fault-Tolerance Approach for Deeply Scaled Memories.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020

2019
GreenChip: A tool for evaluating holistic sustainability of modern computing systems.
Sustain. Comput. Informatics Syst., 2019

Yielding optimized dependability assurance through bit inversion.
Integr., 2019

PREMSim: A Resilience Framework for Modeling Traditional and Emerging Memory Reliability.
Proceedings of the 27th IEEE International Symposium on Modeling, 2019

The Power of Orthogonality.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Toward Secure, Reliable, and Energy Efficient Phase-change Main Memory with MACE.
Proceedings of the Tenth International Green and Sustainable Computing Conference, 2019

Leveraging Transverse Reads to Correct Alignment Faults in Domain Wall Memories.
Proceedings of the 49th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2019

Predicting Single Event Effects in DRAM.
Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019

2018
Data Block Partitioning Methods to Mitigate Stuck-At Faults in Limited Endurance Memories.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Racetrack Queues for Extremely Low-Energy FIFOs.
IEEE Trans. Very Large Scale Integr. Syst., 2018

RETROFIT: Fault-Aware Wear Leveling.
IEEE Comput. Archit. Lett., 2018

Counter Advance for Reliable Encryption in Phase Change Memory.
IEEE Comput. Archit. Lett., 2018

Achieving Secure, Reliable, and Sustainable Next Generation Computing Memories.
Proceedings of the Ninth International Green and Sustainable Computing Conference, 2018

Dark Silicon Considered Harmful: A Case for Truly Green Computing.
Proceedings of the Ninth International Green and Sustainable Computing Conference, 2018

2017
Mitigating bitline crosstalk noise in DRAM memories.
Proceedings of the International Symposium on Memory Systems, 2017

Yoda: Judge Me by My Size, Do You?
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Dynamic partitioning to mitigate stuck-at faults in emerging memories.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Sustainable IC design and fabrication.
Proceedings of the Eighth International Green and Sustainable Computing Conference, 2017

Sustainable fault management and error correction for next-generation main memories.
Proceedings of the Eighth International Green and Sustainable Computing Conference, 2017

Holistic energy efficient crosstalk mitigation in DRAM.
Proceedings of the Eighth International Green and Sustainable Computing Conference, 2017

2016
Improving Bit Flip Reduction for Biased and Random Data.
IEEE Trans. Computers, 2016

Holistically evaluating the environmental impacts in modern computing systems.
Proceedings of the Seventh International Green and Sustainable Computing Conference, 2016

Modeling STT-RAM fabrication cost and impacts in NVSim.
Proceedings of the Seventh International Green and Sustainable Computing Conference, 2016

2015
MSCS: Multi-hop Segmented Circuit Switching.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Domain-wall memory buffer for low-energy NoCs.
Proceedings of the 52nd Annual Design Automation Conference, 2015


  Loading...