Stephen Longofono

Orcid: 0000-0002-5237-8705

According to our database1, Stephen Longofono authored at least 11 papers between 2019 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Links

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Bibliography

2023
Toward Comprehensive Shifting Fault Tolerance for Domain-Wall Memories With PIETT.
IEEE Trans. Computers, April, 2023

2022
Brain-inspired Cognition in Next-generation Racetrack Memories.
ACM Trans. Embed. Comput. Syst., November, 2022

Pinning Fault Mode Modeling for DWM Shifting.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

CORUSCANT: Fast Efficient Processing-in-Racetrack Memories.
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

Virtual Coset Coding for Encrypted Non-Volatile Memories with Multi-Level Cells.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

2021
A CASTLE With TOWERs for Reliable, Secure Phase-Change Memory.
IEEE Trans. Computers, 2021

PIRM: Processing In Racetrack Memories.
CoRR, 2021

Tuning Memory Fault Tolerance on the Edge.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

2019
PREMSim: A Resilience Framework for Modeling Traditional and Emerging Memory Reliability.
Proceedings of the 27th IEEE International Symposium on Modeling, 2019

Toward Secure, Reliable, and Energy Efficient Phase-change Main Memory with MACE.
Proceedings of the Tenth International Green and Sustainable Computing Conference, 2019

Predicting Single Event Effects in DRAM.
Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019


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