Erik Brunvand

Orcid: 0000-0001-8881-927X

According to our database1, Erik Brunvand authored at least 70 papers between 1989 and 2023.

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Bibliography

2023
NSF Integrated Circuit Research, Education and Workforce Development Workshop Final Report.
CoRR, 2023

2022
Mach-RT: A Many Chip Architecture for High Performance Ray Tracing.
IEEE Trans. Vis. Comput. Graph., 2022

2021
Navigating the Seismic Shift of Post-Moore Computer Systems Design.
IEEE Micro, 2021

2020
Hardware-Accelerated Dual-Split Trees.
Proc. ACM Comput. Graph. Interact. Tech., 2020

2019
GreenChip: A tool for evaluating holistic sustainability of modern computing systems.
Sustain. Comput. Informatics Syst., 2019

Extending Student Labs with SMT Circuit Implementation.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Mach-RT: A Many Chip Architecture for Ray Tracing.
Proceedings of the High-Performance Graphics 2019, 2019

2018
A detailed study of ray tracing performance: render time and energy cost.
Vis. Comput., 2018

Time Interval Ray Tracing for Motion Blur.
IEEE Trans. Vis. Comput. Graph., 2018

Dark Silicon Considered Harmful: A Case for Truly Green Computing.
Proceedings of the Ninth International Green and Sustainable Computing Conference, 2018

SimTRaX: Simulation Infrastructure for Exploring Thousands of Cores.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

2017
Making Noise: Using Sound-Art to Explore Technological Fluency.
Inroads, 2017

Power and energy implications of misunderstanding DRAM.
Proceedings of the Eighth International Green and Sustainable Computing Conference, 2017

Sustainable IC design and fabrication.
Proceedings of the Eighth International Green and Sustainable Computing Conference, 2017

Dual streaming for hardware-accelerated ray tracing.
Proceedings of High Performance Graphics, 2017

2016
Leveraging CS Teachable Moments in the Maker Movement (Abstract Only).
Proceedings of the 47th ACM Technical Symposium on Computing Science Education, 2016

Holistically evaluating the environmental impacts in modern computing systems.
Proceedings of the Seventh International Green and Sustainable Computing Conference, 2016

2015
Memory Considerations for Low Energy Ray Tracing.
Comput. Graph. Forum, 2015

Using surface-mount components in an embedded systems lab.
Proceedings of the Workshop on Computer Architecture Education, 2015

A noise-based curriculum for technological fluency.
Proceedings of the Special Interest Group on Computer Graphics and Interactive Techniques Conference, 2015

Technological fluency through circuit bending.
Proceedings of the 2015 IEEE International Conference on Microelectronics Systems Education, 2015

Computational Thinking Meets Design Thinking: Technology and Arts Collaborations.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

2014
Why graphics programmers need to know about DRAM.
Proceedings of the Special Interest Group on Computer Graphics and Interactive Techniques Conference, 2014

Speculatorum oculi.
Proceedings of the Special Interest Group on Computer Graphics and Interactive Techniques Conference, 2014

2013
Lights! speed! action!: fundamentals of physical computing for programmers.
Proceedings of the International Conference on Computer Graphics and Interactive Techniques, 2013

Arts/tech collaboration with embedded systems and kinetic art.
Proceedings of the International Conference on Computer Graphics and Interactive Techniques, 2013

Drawing machines: exploring embedded system programming and hardware with an artistic flair (abstract only).
Proceedings of the 44th ACM Technical Symposium on Computer Science Education, 2013

An Energy and Bandwidth Efficient Ray Tracing Architecture.
Proceedings of the High-Performance Graphics 2013, 2013

2012
Fast, effective BVH updates for animated scenes.
Proceedings of the Symposium on Interactive 3D Graphics and Games, 2012

2011
Kinetic art and embedded systems: a natural collaboration.
Proceedings of the 42nd ACM technical symposium on Computer science education, 2011

Games as motivation in computer design courses: I/O is the key.
Proceedings of the 42nd ACM technical symposium on Computer science education, 2011

2010
Hardware prediction of OS run-length for fine-grained resource customization.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2010

Improving Server Performance on Multi-cores via Selective Off-Loading of OS Functionality.
Proceedings of the Computer Architecture, 2010

Efficient MIMD architectures for high-performance ray tracing.
Proceedings of the 28th International Conference on Computer Design, 2010

2009
TRaX: A Multicore Hardware Architecture for Real-Time Ray Tracing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

OS execution on multi-cores: is out-sourcing worthwhile?
ACM SIGOPS Oper. Syst. Rev., 2009

Hardware-accelerated gradient noise for graphics.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

2008
Fast ray tracing and the potential effects on graphics and gaming courses.
Comput. Graph., 2008

TRaX: A Multi-Threaded Architecture for Real-Time Ray Tracing.
Proceedings of the IEEE Symposium on Application Specific Processors, 2008

2007
Rethinking graphics and gaming courses because of fast ray tracing.
Proceedings of the International Conference on Computer Graphics and Interactive Techniques, 2007

2005
Design of a cell library for asynchronous microengines.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

2004
ARCS: an architectural level communication driven simulator.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

2003
Self-Timed Design with Dynamic Domino Circuits.
Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

Using dynamic domino circuits in self-timed systems.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

2000
High-Level Asynchronous System Design Using the ACK Framework.
Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2000

1999
Peephole optimization of asynchronous macromodule networks.
IEEE Trans. Very Large Scale Integr. Syst., 1999

Impulse: Building a Smarter Memory Controller.
Proceedings of the Fifth International Symposium on High-Performance Computer Architecture, 1999

Practical Advances in Asynchronous Design and in Asynchronous/Synchronous Interfaces.
Proceedings of the 36th Conference on Design Automation, 1999

1998

1997
Critical hazard free test generation for asynchronous circuits.
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

ACT: A DFT Tool for Self-Timed Circuits.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

Practical Advances in Asynchronous Design.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

1996
Self-Timed Design in GaAs - Case Study of a High-Speed, Parallel Multiplier.
IEEE Trans. Very Large Scale Integr. Syst., 1996

Fred: an architecture for a self-timed decoupled computer.
Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '96), 1996

1995
A partial scan methodology for testing self-timed circuits.
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

Precise exception handling for a self-timed processor.
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

Automatic rapid prototyping of semi-custom VLSI circuits using Actel FPGAs.
Proceedings of the 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), 1995

DFT for fast testing of self-timed control circuits.
Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

Testing self-timed circuits using partial scan.
Proceedings of the Second Working Conference on Asynchronous Design Methodologies, 1995

Low latency self-timed flow-through FIFOs.
Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI '95), 1995

1994
Designing self-timed systems using concurrent programs.
J. VLSI Signal Process., 1994

A correctness criterion for asynchronous circuit validation and optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Performance Analysis and Optimization of Asynchronous Circuits.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

Testing micropipelines.
Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems, 1994

1993
Using FPGAs to implement self-timed systems.
J. VLSI Signal Process., 1993

Guest editors' introduction to the special issue on asynchronous systems.
Integr., 1993

1992
A Comparison of Self-Timed Design Using FPGA, CMOS, and GaAs Technologies.
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

Using FPLs to Prototoype a Self-Timed Computer.
Proceedings of the Field-Programmable Gate Arrays: Architectures and Tools for Rapid Prototyping, Second International Workshop on Field-Programmable Logic and Applications, Vienna, Austria, August 31, 1992

1991
An Integrated Environment for the Design and Simulation of Self-Timed Systems.
Proceedings of the VLSI 91, 1991

1989
Translating concurrent programs into delay-insensitive circuits.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989


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