Dongil Lee

Orcid: 0000-0002-2004-2123

According to our database1, Dongil Lee authored at least 15 papers between 2015 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2025
An Offset Compensated Charge Transfer Pre-Sensing Bitline Sense Amplifier.
IEEE J. Solid State Circuits, April, 2025

2024
An Offset-Compensated Charge-Transfer Pre-Sensing Bit-Line Sense-Amplifier for Low-Voltage DRAM.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2020
A 10.8 Gb/s Quarter-Rate 1 FIR 1 IIR Direct DFE With Non-Time-Overlapping Data Generation for 4: 1 CMOS Clockless Multiplexer.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

2019
A 0.9-V 12-Gb/s Two-FIR Tap Direct DFE With Feedback-Signal Common-Mode Control.
IEEE Trans. Very Large Scale Integr. Syst., 2019

A 12 Gb/s 1.59 mW/Gb/s Input-Data-Jitter-Tolerant Injection-Type CDR With Super-Harmonic Injection-Locking in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

A 0.87 V 12.5 Gb/s Clock-Path Feedback Equalization Receiver with Unfixed Tap Weighting Property in 65 nm CMOS.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

2018
A 0.65-V, 11.2-Gb/s Power Noise Tolerant Source-Synchronous Injection-Locked Receiver With Direct DTLB DFE.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A 10-Gb/s Reference-Less Baud-Rate CDR for Low Power Consumption With the Direct Feedback Method.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

2017
An Input Data and Power Noise Inducing Clock Jitter Tolerant Reference-Less Digital CDR for LCD Intra-Panel Interface.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

2016
A 21%-Jitter-Improved Self-Aligned Dividerless Injection-Locked PLL With a VCO Control Voltage Ripple-Compensated Phase Detector.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

RhoanaNet Pipeline: Dense Automatic Neural Annotation.
CoRR, 2016

Standard monomials for temperley-lieb algebras.
ACM Commun. Comput. Algebra, 2016

2015
Standard monomials for the Weyl group <i>F</i><sub>4</sub>.
ACM Commun. Comput. Algebra, 2015

An integrated time register and arithmetic circuit with combined operation for time-domain signal processing.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

An injection locked PLL for power supply variation robustness using negative phase shift phenomenon of injection locked frequency divider.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015


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