Young Hun Seo

According to our database¹, Young Hun Seo authored at least 10 papers between 2009 and 2017.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of five.

Timeline

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In proceedings

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PhD thesis

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On csauthors.net:

Bibliography

2017

A 250-µW 2.4-GHz Fast-Lock Fractional-N Frequency Generation for Ultralow-Power Applications.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2017

2013

A 300-MS/s, 1.76-ps-Resolution, 10-b Asynchronous Pipelined Time-to-Digital Converter With on-Chip Digital Background Calibration in 0.13-µm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2013

2012

A 1.25 ps Resolution 8b Cyclic TDC in 0.13 µm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2012

A 2 GHz Fractional-N Digital PLL with 1b Noise Shaping ΔΣ TDC.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2012

2011

A 1-GHz Digital PLL With a 3-ps Resolution Floating-Point-Number TDC in a 0.18-μm CMOS.

[BibT_eX]

[DOI]

Young Hun Seo

Seon-Kyoo Lee

Jae-Yoon Sim

IEEE Trans. Circuits Syst. II Express Briefs, 2011

2010

A 5 Gb/s Transmitter With a TDR-Based Self-Calibration of Preemphasis Strength.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2010

A 1 GHz ADPLL With a 1.25 ps Minimum-Resolution Sub-Exponent TDC in 0.18 μ m CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2010

A 1GHz ADPLL with a 1.25ps minimum-resolution sub-exponent TDC in 0.18µm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009

A Distortion-Free General Purpose LVDS Driver.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2009

A 650Mb/s-to-8Gb/s referenceless CDR circuit with automatic acquisition of data rate.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

Young Hun Seo

Timeline

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Links

On csauthors.net:

Bibliography

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