Changsik Yoo
Orcid: 0000-0001-7945-5400
According to our database1,
Changsik Yoo
authored at least 61 papers
between 1995 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
13.6 A 16Gb 37Gb/s GDDR7 DRAM with PAM3-Optimized TRX Equalization and ZQ Calibration.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
A 16-Gb/s/Wire 4-Wire Short-Haul Transceiver With Balanced Single-Ended Signaling (BASES) in 28-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, August, 2023
An 8b9b 77.44-Gb/s Noise-Immune Spatial-Delta Coded Transceiver for Short-Reach Memory Interfaces in 28-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2023
A 12-Gb/s Baud-Rate Clock and Data Recovery With 75% Phase-Detection Probability by Precoding and Integration-Hold-Reset Frontend.
IEEE Trans. Circuits Syst. II Express Briefs, February, 2023
DSAC: Low-Cost Rowhammer Mitigation Using In-DRAM Stochastic and Approximate Counting Algorithm.
CoRR, 2023
A 1.1V 6.4Gb/s/pin 24-Gb DDR5 SDRAM with a Highly-Accurate Duty Corrector and NBTI-Tolerant DLL.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 4ns Settling Time FVF-Based Fast LDO Using Bandwidth Extension Techniques for HBM3.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
A 1.01V 8.5Gb/s/pin 16Gb LPDDR5x SDRAM with Self-Pre-Emphasized Stacked-Tx, Supply Voltage Insensitive Rx, and Optimized Clock Using 4th-Generation 10nm DRAM Process for High-Speed and Low-Power Applications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
2022
A 16Gb 9.5Gb/S/pin LPDDR5X SDRAM With Low-Power Schemes Exploiting Dynamic Voltage-Frequency Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm DRAM Process.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2021
Solar Energy-Harvesting Buck-Boost Converter With Battery-Charging and Battery-Assisted Modes.
IEEE Trans. Ind. Electron., 2021
A Reflection and Crosstalk Canceling Continuous-Time Linear Equalizer for High-Speed DDR SDRAM.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
A 3.2-12.8Gb/s Duty-Cycle Compensating Quadrature Error Corrector for DRAM Interfaces, With Fast Locking and Low Power Characteristics.
Proceedings of the 47th ESSCIRC 2021, 2021
2020
A 6-Gb/s Wireline Receiver With Intrapair Skew Compensation and Three-Tap Decision-Feedback Equalizer in 28-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2020
Time-Domain Operational Amplifier With Voltage-Controlled Oscillator and Its Application to Active-RC Analog Filter.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
2019
A Current-Mode Hysteretic Buck Converter With Multiple-Reset RC-Based Inductor Current Sensor.
IEEE Trans. Ind. Electron., 2019
A 4-MHz Bandwidth Continuous-Time Sigma-Delta Modulator With Stochastic Quantizer and Digital Accumulator.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
IEEE J. Solid State Circuits, 2019
Time-Based Digital LDO Regualtor with Fractionally Controlled Power Transistor Strength and Fast Transient Response.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
2018
Continuous-time linear equalizer with automatic boosting gain adaptation and input offset cancellation.
Int. J. Circuit Theory Appl., 2018
A 10MHz time-domain-controlled current-mode buck converter with 8.5% to 93% switching duty cycle.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2017
A simultaneously bidirectional inductively coupled link in a 0.13-µm CMOS technology.
Int. J. Circuit Theory Appl., 2017
IEICE Electron. Express, 2017
IEEE Access, 2017
2016
Quasi-Resonant (QR) Controller With Adaptive Switching Frequency Reduction Scheme for Flyback Converter.
IEEE Trans. Ind. Electron., 2016
Int. J. Circuit Theory Appl., 2016
A HDMI-to-MHL video format conversion system-on-chip (SoC) for mobile handset in a 130-nm CMOS technology.
Proceedings of the IEEE International Conference on Consumer Electronics, 2016
2015
IEEE Trans. Circuits Syst. II Express Briefs, 2015
Int. J. Circuit Theory Appl., 2015
Int. J. Circuit Theory Appl., 2015
Int. J. Circuit Theory Appl., 2015
Int. J. Circuit Theory Appl., 2015
An analog sigma-delta modulator with shared operational amplifier for low-power class-D audio amplifier.
IEICE Electron. Express, 2015
2014
IEEE Trans. Circuits Syst. II Express Briefs, 2014
A fast automatic frequency calibration technique for a 2-6 GHz frequency synthesizer.
Int. J. Circuit Theory Appl., 2014
A 1.5-5.0 Gb/s clock and data recovery circuit with dual-PFD phase-rotating phase locked loop.
IEICE Electron. Express, 2014
Data and edge decision feedback equalizer with >1.0-UI timing margin for both data and edge samples.
IEICE Electron. Express, 2014
Digital phase locked loop (DPLL) with offset dithered bang-bang phase detector (BBPD) for bandwidth control.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014
2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
A Class-D Amplifier With Pulse Code Modulated (PCM) Digital Input for Digital Hearing Aid.
IEEE J. Solid State Circuits, 2013
2012
Load-Independent Current Control Technique of a Single-Inductor Multiple-Output Switching DC-DC converter.
IEEE Trans. Circuits Syst. II Express Briefs, 2012
Measurement of Intersymbol Interference Jitter by Fractional Oversampling for Adaptive Equalization.
IEEE Trans. Circuits Syst. II Express Briefs, 2012
2011
A 2x2 MIMO Tri-Band Dual-Mode Direct-Conversion CMOS Transceiver for Worldwide WiMAX/WLAN Applications.
IEEE J. Solid State Circuits, 2011
A 20-MHz Bandwidth Continuous-Time Sigma-Delta Modulator With Jitter Immunity Improved Full Clock Period SCR (FSCR) DAC and High-Speed DWA.
IEEE J. Solid State Circuits, 2011
2010
A 1.62/2.7Gbps clock and data recovery with pattern based frequency detector for displayport.
IEEE Trans. Consumer Electron., 2010
Spread spectrum clock generation for reduced electro-magnetic interference in consumer electronics devices.
IEEE Trans. Consumer Electron., 2010
Int. J. Circuit Theory Appl., 2010
A 2×2 MIMO tri-band dual-mode CMOS transceiver for worldwide WiMAX/WLAN applications.
Proceedings of the 36th European Solid-State Circuits Conference, 2010
2009
A 5-Gbit/s Clock- and Data-Recovery Circuit With 1/8-Rate Linear Phase Detector in 0.18-μm CMOS Technology.
IEEE Trans. Circuits Syst. II Express Briefs, 2009
2007
IEEE Trans. Consumer Electron., 2007
2005
IEEE Trans. Consumer Electron., 2005
Active-RC channel selection filter tunable from 6 kHz to 18 MHz for software-defined radio.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
A 1.2V, 10MHz, low-pass Gm-C filter with Gm-cells based on triode-biased MOS and passive resistor in 0.13μm CMOS technology.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
2004
A 1.8-V 700-mb/s/pin 512-mb DDR-II SDRAM with on-die termination and off-chip driver calibration.
IEEE J. Solid State Circuits, 2004
Digital delay locked loop with open-loop digital duty cycle corrector for 1.2Gb/s/pin double data rate SDRAM.
Proceedings of the 33rd European Solid-State Circuits Conference, 2004
2002
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002
2001
IEEE J. Solid State Circuits, 2001
1999
IEEE Trans. Consumer Electron., 1999
IEEE J. Solid State Circuits, 1999
1998
IEEE J. Solid State Circuits, 1998
1995
IEEE J. Solid State Circuits, May, 1995