Sangjoon Hwang
Affiliations:- Samsung Electronics, Memory Division, Hwasung, Korea
- Korea University, Department of Electrical Engineering, Seoul, South Korea
According to our database1,
Sangjoon Hwang authored at least 34 papers
between 2005 and 2026.
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Bibliography
2026
Pangaea v2: CXL-Based Disaggregated Memory System Architecture for Cloud-Native Orchestration.
IEEE Trans. Computers, April, 2026
S-Tiering: A Unified HW/SW Solution for Memory Tiering Based on the Standard CXL Hotness Monitoring Unit.
IEEE Trans. Computers, April, 2026
15.10 A Vertical-Cell-Transistor-Based 4F<sup>2</sup> DRAM with Cell-on-Peripheral Architecture Using Wafer-to-Wafer Hybrid Copper Bonding.
Proceedings of the IEEE International Solid-State Circuits Conference, 2026
A 16Gb 12.8Gb/s LPDDR6 SDRAM with 12-DQ/Sub-Channel Wide NRZ Signaling and Enhanced Reliability by Per-Row Activation Counting and Meta-Data Scheme.
Proceedings of the IEEE International Solid-State Circuits Conference, 2026
15.6 A 36GB 3.3TB/S HBM4 DRAM with Per-Channel TSV RDQS Auto Calibration and Fully-Programmable MBIST.
Proceedings of the IEEE International Solid-State Circuits Conference, 2026
2025
IEEE J. Solid State Circuits, April, 2025
IEEE J. Solid State Circuits, January, 2025
A Fine and Massive Test Methodology for Analyzing Core Characteristics in the Development of Next Generation DRAM.
Proceedings of the IEEE International Test Conference, 2025
30.3 A 24Gb 42.5Gb/s GDDR7 DRAM with Low-Power WCK Distribution, an RC-Optimized Dual-Emphasis TX, and Voltage/Time-Margin-Enhanced Power Reduction.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025
A 16Gb 12.7Gb/s/pin LPDDR5-Ultra-Pro DRAM with 4-Phase Self-Calibration and AC-Coupled Transceiver Equalization in a 5<sup>th</sup>-Generation 10nm DRAM Process.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025
Improvement of IGZO BTI for DRAM Cell application by heat treatment and recovery effect.
Proceedings of the IEEE International Reliability Physics Symposium, 2025
2024
An Offset-Compensated Charge-Transfer Pre-Sensing Bit-Line Sense-Amplifier for Low-Voltage DRAM.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5<sup>th</sup>-Generation 10nm DRAM Process.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
13.6 A 16Gb 37Gb/s GDDR7 DRAM with PAM3-Optimized TRX Equalization and ZQ Calibration.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
A Single-Ended Offset-Compensating Bit-Line Sense-Amplifier with Ground Precharge and Charge Transfer Pre sensing for Sub-1V DRAM.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024
2023
A 16 GB 1024 GB/s HBM3 DRAM With Source-Synchronized Bus Design and On-Die Error Control Scheme for Enhanced RAS Features.
IEEE J. Solid State Circuits, 2023
A 16-Gb T-Coil-Based GDDR6 DRAM With Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus Achieving 27-Gb/s/Pin in NRZ.
IEEE J. Solid State Circuits, 2023
DSAC: Low-Cost Rowhammer Mitigation Using In-DRAM Stochastic and Approximate Counting Algorithm.
CoRR, 2023
2022
A 16 GB 1024 GB/s HBM3 DRAM with On-Die Error Control Scheme for Enhanced RAS Features.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
A 16Gb 27Gb/s/pin T-coil based GDDR6 DRAM with Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
A 16Gb 9.5Gb/S/pin LPDDR5X SDRAM With Low-Power Schemes Exploiting Dynamic Voltage-Frequency Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm DRAM Process.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2021
A Reflection and Crosstalk Canceling Continuous-Time Linear Equalizer for High-Speed DDR SDRAM.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
Proceedings of the IEEE Hot Chips 33 Symposium, 2021
2020
A 1.8 Gb/s/pin 16Tb NAND Flash Memory Multi-Chip Package with F-Chip of Toggle 4.0 Specification for High Performance and High Capacity Storage Systems.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
13.1 A 1Tb 4b/cell NAND Flash Memory with tPROG=2ms, tR=110µs and 1.2Gb/s High-Speed IO Rate.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
A 512Gb 3-bit/Cell 3D 6<sup>th</sup>-Generation V-NAND Flash Memory with 82MB/s Write Throughput and 1.2Gb/s Interface.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2017
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017
2008
An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion.
IEEE J. Solid State Circuits, 2008
J. Comput., 2008
IEICE Electron. Express, 2008
2007
An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
A New Organic Thin-Film Transistor Based Current-Driving Pixel Circuit for Active-Matrix Organic Light-Emitting Displays.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
2005
IEEE J. Solid State Circuits, 2005